mendozaulises
Member level 3
vcs incdir
Hi all, I am new to synopsys vcs and I'm having trouble when trying to compile.
Let's say I have my RTL design in a folder named rtl.
Say that I have some BFM's a a folder named bfm.
And finally let's say I create a testbench in a folder named testbench, which instances a top module from rtl folder and a bfm from bfm folder.
How can I compile bfms and rtl in separate libraries in vcs????
In QuestaSim I can do this:
//Create the libraries
> vlib rtl_lib
> vlib bfm_lib
//Compile rtl files into rtl_lib library
> vlog rtl/*.v -work rtl_lib
//Compile bfm files into bfm_lib
> vlog bfm/*.v -work bfm_lib
/*Compile system-verilog files from testbench directories, and look for undeclared modules at rtl_lib and bfm_lib libraries*/
>vlog testbench/*.sv -sv -L rtl_lib -L bfm_lib
The question again is, is there a similar mechanism in synopsys vcs??
How can i do it?
Thanks in Advance,
Hi all, I am new to synopsys vcs and I'm having trouble when trying to compile.
Let's say I have my RTL design in a folder named rtl.
Say that I have some BFM's a a folder named bfm.
And finally let's say I create a testbench in a folder named testbench, which instances a top module from rtl folder and a bfm from bfm folder.
How can I compile bfms and rtl in separate libraries in vcs????
In QuestaSim I can do this:
//Create the libraries
> vlib rtl_lib
> vlib bfm_lib
//Compile rtl files into rtl_lib library
> vlog rtl/*.v -work rtl_lib
//Compile bfm files into bfm_lib
> vlog bfm/*.v -work bfm_lib
/*Compile system-verilog files from testbench directories, and look for undeclared modules at rtl_lib and bfm_lib libraries*/
>vlog testbench/*.sv -sv -L rtl_lib -L bfm_lib
The question again is, is there a similar mechanism in synopsys vcs??
How can i do it?
Thanks in Advance,