# Synopsys VCS library creation

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#### mendozaulises

##### Member level 3
vcs incdir

Hi all, I am new to synopsys vcs and I'm having trouble when trying to compile.

Let's say I have my RTL design in a folder named rtl.
Say that I have some BFM's a a folder named bfm.
And finally let's say I create a testbench in a folder named testbench, which instances a top module from rtl folder and a bfm from bfm folder.

How can I compile bfms and rtl in separate libraries in vcs????

In QuestaSim I can do this:
//Create the libraries
> vlib rtl_lib
> vlib bfm_lib
//Compile rtl files into rtl_lib library
> vlog rtl/*.v -work rtl_lib
//Compile bfm files into bfm_lib
> vlog bfm/*.v -work bfm_lib

/*Compile system-verilog files from testbench directories, and look for undeclared modules at rtl_lib and bfm_lib libraries*/
>vlog testbench/*.sv -sv -L rtl_lib -L bfm_lib

The question again is, is there a similar mechanism in synopsys vcs??
How can i do it?

#### amnsgk

##### Newbie level 4
simv options

VCS is easy to use and is only two step.

First step:
compilation and generation of simulation executable

Second step:
Run the simulation.

Hence the option you are looking for is not available in VCS. You just need to do the following:

For compilation:
vcs -sverilog tb/*.sv bfm/*.v rtl*.v +incdir+tb+bfm+rtl
Along with this command you can use other options which are required for your testcase.

For imulation:
./simv
You can also use the required runtime options with the executable simv.

You can refer the VCS Userguide in $VCS_HOME/doc/UserGuide/vcs.pdf for more details. Thanks. ### mendozaulises Points: 2 Helpful Answer Positive Rating #### mendozaulises ##### Member level 3 vcs library There must be an option. I found out that the command vlogan -work mylib would do what I am looking for, however a vcs error shows. Error: undefined undefinedPhase vhdl-877 Environment variable$SYNOPSYS_SIM not set

Error-[ILWOR] Incorrect Logical Worklib or Reflib
logical lib: "mylib"

Is this a problem of licensing?
it seems I am still missing the command to create the library (the equivalent of vlib in Questa).

Any out there that can help?

#### balajivenu

##### Newbie level 1
synopsys vcs user guide

Hi,

There is a command by name "show_setup"
This will tell you what values the environment variables will take.

However, i am unable to change it the place i want it.
also, the work library creation is not straight forward.

Anyway, i tried compiling and running the ./simv file.
However no gui opened, it just told its run and then exited.

Anybody out there, who knows how to create a library and compile files and elaborate it there, please let me know

Balaji

#### aji_vlsi

vcs vlogan help

mendozaulises said:
There must be an option.

I found out that the command vlogan -work mylib would do what I am looking for, however a vcs error shows.

Error: undefined undefinedPhase vhdl-877
Environment variable \$SYNOPSYS_SIM not set

Error-[ILWOR] Incorrect Logical Worklib or Reflib
logical lib: "mylib"

Is this a problem of licensing?
it seems I am still missing the command to create the library (the equivalent of vlib in Questa).

Any out there that can help?

Using vlogan is so c alled UUM flow within Synopsys tools. It is needed/recommended only if you have mixed language designs. For pure Verilog/SystemVerilog simply do:

Code:
vcs -sverilog -f flist -debug_all
./simv -gui

HTH
Ajeetha, CVC
www.noveldv.com

#### dhaval4987

##### Full Member level 3
so, does it generate the verilog libraries for standard cells just from the transistor models? is there any tool that does it?

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