Hi all if u worked on prime power please read and help me.
When i am calculating power for a module which has some submodules inside, it is telling unable to resolve references & creating black boxes. I am using the following script for calculating power
set search_path "."
set link_path "* /home/sagar_mp/main fsa0m_a_generic_core_tt1p8v25c.db"
set target_library "/home/sagar_mp/main/synopsys/fsa0m_a_generic_core_tt1p8v25c.db"
set link_library "/home/sagar_mp/main/synopsys/fsa0m_a_generic_core_tt1p8v25c.db"
set symbol_library "/home/sagar_mp/main/synopsys/fsa0m_a_generic_core.sdb"
read_verilog /home/sagar_mp/main/subbytes3_net.v
current_design subbytes3
link
read_vcd -strip tb_subbytes3/t1 /home/sagar_mp/main/subbytes3_vcd.vcd
calculate_power
report_power -file subbytes3_pwr
here my main module is subbytes3. It is all combinational logic and it has 4 internal modules. I wrote all (main module & submodules) in a single file & it is inside /home/sagar_mp/main.
Subbytes3_net is my netlist generated by synopsys Design Compiler.
When i give link command it is telling unable to resolve references. I tried by writing all submodules in different files and used `include directive in the main module subbytes3, still problem is not solved.
Please give me solution to solve this problem. If u want any details ask me, i will give you
Thank you