synopsys parallel case

[they]

when running sythesis for RTLs with Design Compiler, for a case statement, if we want it to run parallelly, is it correct if we do like below:

case /* synopsys parallel_case */

or should be

case /* synopsys_parallel_case */

 

[sxqzj]

synopsys full case

since you use the directives i think its may run that way!

 

[they]

synopsys parallel_case

since you use the directives i think its may run that way!

I mean which of the two following directive is correct?

case /* synopsys parallel_case */

or should be

case /* synopsys_parallel_case */

I heard somebody says that the latest version of Design Compiler will treat all case statement as parallel even the parallel case directive is not attached, is it true?

 

[eda_wiz]

synopsys full_case parallel_case

correct usage is ....
// synopsys parallel_case

 

[EleApollo]

synopsys full_case

The first is right!
The second will be interpret as a comment

 

[linuxluo]

synopsys full case parallel case

hi,
According to RMM second version and some paper from snug, dont use full_parallel , it may cause simulation difference between pre and post synthesis.

 

[zzczx]

full case parallel case

seems only //synopsys xxxx directive format .
I haven't seen any /*synopsys xxx */ directive.
In the snug papaer :
"full_case parallel_case", the Evil Twins of Verilog Synthesis,the author suggested that it is better to code a full and parallel case statement than it is to use directives to make up for poor coding practices. And I agree with him.

 

[they]

synopsys parallel

I found some weird problem,

for example, within a RTL design, there are lot of case statement, which I put the "//synopsys parallel_case" directive to all of them.

But during synthesis, some warnings came out which showed that some case statements (not all of them) are not parallel case. As the result, the timing of the synthesis become very bad.

I tried to remove those directive from the case statements with warning, and the warnings disappear when i re-synthesize the RTL and the timing constraint can be met.

Can anybody explain it?

 

[they]

difference between full case and parallel case

seems only //synopsys xxxx directive format .
I haven't seen any /*synopsys xxx */ directive.
In the snug papaer :
"full_case parallel_case", the Evil Twins of Verilog Synthesis,the author suggested that it is better to code a full and parallel case statement than it is to use directives to make up for poor coding practices. And I agree with him.

Hi zzczx,
you mean directive "/* synopsys xxxx */" and "//synopsys xxx " will produce different result?

 

[zhangpengyu]

parallel case full case

// synopsys parallel_case
is right!

 

[zzczx]

full case and parallel case

Hi zzczx,
you mean directive "/* synopsys xxxx */" and "//synopsys xxx " will produce different result?

I am sorry.I test the /* synopsys xx */ and //synopsys just now,and they are both supported by dc.
//synopsys full_case parallel_case
==============================================
| Line | full/ parallel |
===============================================
| 19 | user/user |
===============================================

/*synopsys full_case parallel_case*/
===============================================
| Line | full/ parallel |
===============================================
| 19 | user/user |
===============================================

//no synopsys directive
===============================================
| Line | full/ parallel |
===============================================
| 19 | no/auto |
===============================================

 

[they]

synopsys full and parallel cases

I found some weird problem,

for example, within a RTL design, there are lot of case statement, which I put the "//synopsys parallel_case" directive to all of them.

But during synthesis, some warnings came out which showed that some case statements (not all of them) are not parallel case. As the result, the timing of the synthesis become very bad.

I tried to remove those directive from the case statements with warning, and the warnings disappear when i re-synthesize the RTL and the timing constraint can be met.

Can anybody explain it?

I found some explaination from synopsys website about the warning occured.

>Problem:
>
>
>During elaboration, Design Compiler reports the following message:>
>
>Warning: /home/design/test.v:12: Case statement is not a parallel >case.
>(ELAB-910)
>
>The case statement in question is indeed parallel, so this warning >message
>should not appear.
>
>Explanation:
>
>
>The ELAB-910 message appears in some cases when the parallel_case
>pragma is used for a case statement which is already parallel.
>
>Workaround:
>
>
>The parallel_case pragma can be removed from the case statement in
>question to avoid the message.
>


By the way, heard somebody said that the new version of DC will treat all the case statement as parallel case even there is no parallel case directive used, is it true?
As i try with some simple examples, there is no difference between the synthesis result of the one with parallel case directive and another one without.

 

[zzczx]

synopsys case parallel

By the way, heard somebody said that the new version of DC will treat all the case statement as parallel case even there is no parallel case directive used, is it true?
As i try with some simple examples, there is no difference between the synthesis result of the one with parallel case directive and another one without.

how did you carry the test?In the following situation:

case (4b'sel)
1???:statement;
?1??:statement;
??1?:statement;
???1:statement;
defalt:statement;
endcase.

Is the result same whether with the parallel case directive or not?
Since my software's version is older, I can't test it.

 

[they]

parallel case directive

By the way, heard somebody said that the new version of DC will treat all the case statement as parallel case even there is no parallel case directive used, is it true?
As i try with some simple examples, there is no difference between the synthesis result of the one with parallel case directive and another one without.

how did you carry the test?In the following situation:

case (4b'sel)
1???:statement;
?1??:statement;
??1?:statement;
???1:statement;
defalt:statement;
endcase.

Is the result same whether with the parallel case directive or not?
Since my software's version is older, I can't test it.

The version of DC I am using is 2003.06-SP1, I ran synthesis for a module which contains two case, and each case contains 4 to 5 statements. Both of the synthesis (the module with and without the "//synopsys parallel_case" directive) result , in terms of timing or area are same.