Synopsys Design Compiler

[njr@1]

Dear all

When I try to synthesis the Design ware example in DC and give the clk some period why am I not able to see the clk period in the timing report or the report_qor! it says critical path slack as uninit and critical psth clk period as n/a !

Please let me know.

Thank you

 

[sharath666]

How are you giving the clk "some period"?

 

[njr@1]

create_clock "clk" -period 5 [get_ports clk] in this way.

 

[sharath666]

This is correct. But are you know whether there are valid paths within the design that use this clock?

 

[njr@1]

yes. There are valid path.

 

[sharath666]

Then you can try a report_timing command on a valid path..See what it reports..