Synopsys Design Compiler: Setting a maximum critical path delay on sequential circuits

[natasha_a]

I have a couple of designs written in Verilog that I'm trying to synthesize with Synopsys DC Compiler. Specifically, I would like to maintain a 1ns upper bound on my critical path delay (CPD) on my designs — I have been able to successfully synthesize these designs with yosys (open source RTL synthesis tool) and meet this constraint.

I've tried setting a variety of parameters in a tcl script that I am using for synthesis of my Verilog modules, but none seem to be enforcing this upper bound on my CPD. Just to name a few things I have attempted: I've used the compile_ultra command, with and without the -retime flag (and the set_optimize_registers flag preceding this). I've tried using the set_max_delay command on all clocked paths, and any path from all inputs to all outputs. I've tried various settings of the clock period, to see whether increasing/decreasing the clock period from 1ns could help things.

Unfortunately, none of these has worked. Consistently, the DC compiler indicates that the timing slack has been violated and returns a CPD of nearly 4ns. I've been stuck on this issue for some time, and I'm not sure where else to turn to for help. I'm new to this tool, but I've tried reading through large portions of the DC Compiler manual in search of more parameters/commands that may help.

I would really appreciate it if someone had any advice on things that would enforce this 1ns constraint, or some intuition about the tool that could help. Thanks in advance.

 

[ThisIsNotSam]

have you defined a clock period?

 

[natasha_a]

Yes, I've defined a clock period of 1 ns for all clocks in my module.

 

[ThisIsNotSam]

Yes, I've defined a clock period of 1 ns for all clocks in my module.

option 1 - you are doing it wrong and the clock period constraint is not being applied, check your execution logs.
option 2 - the path that seems to violate timing is not a flop-to-flop path, which requires additional constraints

 

[natasha_a]

interesting. in the case that it is option 2, what additional constraints would be required? are these additional parameters/flags that I need to set?
I'll check my logs and post an update.

thanks!

 

[ThisIsNotSam]

set_input_delay and set_output_delay

please post a simple timing report showing all elements in the critical path, it will be easier to debug that way

 

[dormant_bci]

As ThisisNotSam mentioned, you should set the set_input_delay and set_output_delay constraints. What I do when the exact synthesized area doesn't matter is that I input and output everything to and from flip-flops. So, even the input and output combinational logics will be synthesized wrt the clock.