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[SOLVED] synopsys design compiler error: mismatch signals width

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soloktanjung

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Hello friends,

I have problems when analyzing vhdl files in the synopsys design compiler. I do not know why this is happen because I synthesized the same design in virtex4 fpga without a problem. Can anyone please point me out what cause the error below?


Code: 
signal cnt_req 	: std_logic_vector(1 downto 0);

process(clk_i)
begin
	if (clk_i'event and clk_i = '1') then
		if rst_i = '1' then
			cnt_req <= (others => '0');
		else
 			if ctrl_in_wr_en_o_temp = '1' and ctrl_in_sent_i = '1' then 
 				cnt_req <= cnt_req;		
			elsif ctrl_in_wr_en_o_temp = '1' then 
				cnt_req <= cnt_req + '1'; --line 604
			elsif ctrl_in_sent_i = '1' then
				cnt_req <= cnt_req - '1'; --line 606
			end if;
		end if;
	end if;
end process;

This is the errors:

Code: 
Error:  ./HDL/ctrl_in.vhd:604: The lhs width=2 does not match the rhs width=4 of the assignment statement. (ELAB-992)
Error:  ./HDL/ctrl_in.vhd:604: The lhs width=2 does not match the rhs width=4 of the assignment statement. (ELAB-992)
Error:  ./HDL/ctrl_in.vhd:604: The lhs width=4 does not match the rhs width=2 of the assignment statement. (ELAB-992)
Error:  ./HDL/ctrl_in.vhd:606: The lhs width=2 does not match the rhs width=4 of the assignment statement. (ELAB-992)
Error:  ./HDL/ctrl_in.vhd:606: The lhs width=2 does not match the rhs width=4 of the assignment statement. (ELAB-992)
Error:  ./HDL/ctrl_in.vhd:606: The lhs width=4 does not match the rhs width=2 of the assignment statement. (ELAB-992)

Thanks in advance!

Hairo
 

What IEEE packages are you using to perform the addition? Typically, you can not add std_logic_vector with type std_logic.
 

Apparently you are using one of the "lazy engineers" packages like std_logic_unsigned. I would try with "1" or "01" at first instance.
 

Hi,

I tried using "1" and "01" as your suggestion but did not work.

Thanks for the reply. I used this package:

Code: 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

Can you please show me what package I need? And what do you mean by "lazy engineers" packages?

Thanks.

Hairo
 

I checked the definition of std_logic_unsigned and it in fact allows to add std_logic_vector and std_logic. It should work identical to adding a std_logic_vector of "1" or "01". The resuslt length is however identical to the input vector, in so far the problem isn't understandable.

It's may be however necessary to import the underlying std_logic_arith library as well.

I call std_logic_unsigned and std_logic_signed "lazy engineers" libraries, because they are mainly used to avoid typing a few lines of clear type definition in your VHDL code. They are often causing confusion.
 

Hi FvM,

I added the std_logic_arith library but still did not work.

I have similar function (code below) in another file using "lazy engineers packages" without any problem.

Code: 
process(clk_i)
begin
	if (clk_i'event and clk_i = '1') then
		if rst_i = '1' then
			cnt_in <= (others => '0');
		else
			if cnt_tx_in = "11" then
				cnt_in <= (others => '0');	
			elsif ctrl_ack_tx_i = '1' then
				cnt_in <= cnt_in + 1;
			end if;
		end if;
	end if;
end process;

I also found it very strange. Would the errors be from other part of the code in the file?

Thanks.
 

I guess, there's something special in your design, not visible in the posted snippets.

Personally I'm not using Synopsis DC. Sometimes a syntax error is not displayed correctly, resulting in an erroneous message. If the problem isn't obvious, you'll need to modify the source incrementally until the problem disappears respectively shows. Nothing that we can do from a distance.
 

hairo said:
Hello friends,

I have problems when analyzing vhdl files in the synopsys design compiler. I do not know why this is happen because I synthesized the same design in virtex4 fpga without a problem. Can anyone please point me out what cause the error below?


Code: 
signal cnt_req 	: std_logic_vector(1 downto 0);

process(clk_i)
begin
	if (clk_i'event and clk_i = '1') then
		if rst_i = '1' then
			cnt_req <= (others => '0');
		else
 			if ctrl_in_wr_en_o_temp = '1' and ctrl_in_sent_i = '1' then 
 				cnt_req <= cnt_req;		
			elsif ctrl_in_wr_en_o_temp = '1' then 
				cnt_req <= cnt_req + '1'; --line 604
			elsif ctrl_in_sent_i = '1' then
				cnt_req <= cnt_req - '1'; --line 606
			end if;
		end if;
	end if;
end process;

This is the errors:

Code: 
Error:  ./HDL/ctrl_in.vhd:604: The lhs width=2 does not match the rhs width=4 of the assignment statement. (ELAB-992)
Error:  ./HDL/ctrl_in.vhd:604: The lhs width=2 does not match the rhs width=4 of the assignment statement. (ELAB-992)
Error:  ./HDL/ctrl_in.vhd:604: The lhs width=4 does not match the rhs width=2 of the assignment statement. (ELAB-992)
Error:  ./HDL/ctrl_in.vhd:606: The lhs width=2 does not match the rhs width=4 of the assignment statement. (ELAB-992)
Error:  ./HDL/ctrl_in.vhd:606: The lhs width=2 does not match the rhs width=4 of the assignment statement. (ELAB-992)
Error:  ./HDL/ctrl_in.vhd:606: The lhs width=4 does not match the rhs width=2 of the assignment statement. (ELAB-992)

Thanks in advance!

Hairo
Click to expand...

library ieee;
use ieee.std_logic_1164.all
use ieee.numeric_std.all

signal cnt_req : unsigned(1 downto 0)

process (clk_i)
begin
if(clk_i'event and clk_i = '1') then
if rst_i = '1' then
cnt_req <= (others => '0');
else
if ctrl_in_er_en_o_temp = '1' and ctrl_in_sent_i = '1' then
cnt_req <= cnt_req;
elseif ctrl_in_wr_en_0_temp = '1' then
cnt_req <= cnt_req + 1;
elseif ctrl_in_sent_i = '1' then
cnt_req <= cnt_req - 1;
end if;
end if;
end if;
end process;


The issue you are having is directly related to types in VHDL. The other solution is to keep the unofficial libraries and directly type cast the addition and subtraction for example

signal cnt_req : std_logic_vector(1 downto 0);

cnt_req <= std_logic_vector(to_unsigned(cnt_req) + 1);

Please let me know if this resolves your problem.
 
Have you tried without the quotes

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

cnt_req <= cnt_req + 1; --line 604
elsif ctrl_in_sent_i = '1' then
cnt_req <= cnt_req - 1; --line 606

Alex
 

Hello GiuseppeLaPiana,

Thanks for your suggestion. It was very helpful indeed. The error is solved. This the modification that I did according to your suggestion:

Code: 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;

signal cnt_req 	: unsigned(1 downto 0);

process(clk_i)
begin
	if (clk_i'event and clk_i = '1') then
		if rst_i = '1' then
			cnt_req <= (others => '0');
		else
 			if ctrl_in_wr_en_o_temp = '1' and ctrl_in_sent_i = '1' then 
 				cnt_req <= cnt_req;		
			elsif ctrl_in_wr_en_o_temp = '1' then 
				cnt_req <= cnt_req + 1;
			elsif ctrl_in_sent_i = '1' then
				cnt_req <= cnt_req - 1;
			end if;
		end if;
	end if;
end process;

Just curious, why ISE 10.1 did not have any errors and why only in this file Synopsys DC have errors? (which other files have similar addition function).

Anyway, it solve the problems and thanks again for both of you!!!

Hairo

---------- Post added at 17:24 ---------- Previous post was at 17:10 ----------

Hi Alex,

I tried using your suggestion (arith package and + 1) but did not work. I don't know why.

Thanks.

Hairo
 

OK. just checking because all your examples had single or double quotes, it works in ISE, Quartus, modelsim etc

Alex
 

Thank You,

I am glad to see that your problem was resolved. Just remember to always be cautious when using the unofficial std_logic_arith/std_logic_unsigned/std_logic_signed libraries. Remember that numeric_std is the ONLY official IEEE library for arithmetic operations, and it was designed do that it was clear a digital designer meant when inferring complex operations such as addition or subtraction.

As for the question of ISE vs. Synopsys, my guess is that ISE implements a different background synthesizer that resolved your issue. This is a wild guess, as I am not an expert on ISE by any means. I would be interested however in seeing if anyone does have an official answer for this.
 
My explanation is, that Synopsys DC uses a different (incompatible) version of std_logic_unsigned, which is strange, because the library used by the other tools has been originated from Synopsys. I guess, the problem won't occure with reasonable arithmetic types and ieee.numeric_std.
 

synopsys design compiler error

hi..
am also facing problem in design compiler..
me got following error:

constant value required (Error ELAB-922)

and this error is showing in line where i have written if statement> my coding is in VHDL.

so can anybody knows what problem am facing in coding????
 

Please post part of the code that give error and we can give suggestions.

Thanks.
 

hairo said:
Please post part of the code that give error and we can give suggestions.

Thanks.
Click to expand...

this is part of code::(error is in line shown in red colour)


--
--
Code: 
LIBRARY IEEE;
    USE IEEE.STD_LOGIC_1164.ALL;
    USE IEEE.STD_LOGIC_ARITH.ALL;
    
LIBRARY WORK;
    USE WORK.PKG_TYPES.ALL;
    
    ENTITY E_GolumbCoder IS
        PORT
            (
               input_stream:IN STD_LOGIC_VECTOR(INPUT_LENGTH-1 DOWNTO 0);
               reset:IN STD_LOGIC;
               clk:IN STD_LOGIC;
               output_stream:OUT STD_LOGIC_VECTOR(INPUT_LENGTH-1 DOWNTO 0);
               done:OUT STD_LOGIC
            );
    END E_GolumbCoder;
    
    ARCHITECTURE A_GolumbCoder OF E_GolumbCoder IS
        SIGNAL s_count:INTEGER;
        SIGNAL s_output_count:INTEGER;
        SIGNAL s_current_count:INTEGER;
        SIGNAL s_current_mod:INTEGER;
        SIGNAL s_current_div:INTEGER;
        BEGIN
            
            PROCESS(clk)
                VARIABLE v_count:INTEGER;
                VARIABLE v_output_count:INTEGER;
                VARIABLE v_current_count:INTEGER;
                
                VARIABLE v_current_mod:INTEGER;
                VARIABLE v_current_div:INTEGER;
                
                VARIABLE v_current_bit:STD_LOGIC;
                BEGIN
                    
                    s_count <= v_count;
                    s_output_count <= v_output_count;
                    s_current_count <= v_current_count;
                    s_current_mod <= v_current_mod;
                    s_current_div <= v_current_div;
                    
                    IF(clk='1' AND clk'EVENT) THEN
                        IF(reset = '1') THEN
                            v_count := 0;
                            v_output_count := 0;
                            v_current_count := 0;
                            v_current_bit := input_stream(v_count);
                        ELSE
[COLOR="#FF0000"]                            IF(input_stream(v_count) = v_current_bit) THEN
[/COLOR]                                v_current_count := v_current_count + 1;
                            ELSE
                                v_current_bit := input_stream(v_count);
                                --FIND THE CURRENT MOD AND DIV VALUES
                                v_current_mod := v_current_count MOD M;
                                v_current_div := v_current_count / M;
                                
                                --NOW COPY THIS TO OUTPUT STREAM
                                output_stream(v_output_count) <= '1';
                                v_output_count := v_output_count + 1;
                                output_stream(v_output_count+v_current_div-1 DOWNTO v_output_count) <= (OTHERS => '0');
                                v_output_count := v_output_count + v_current_div;
                                output_stream(v_output_count+LOG2M-1 DOWNTO v_output_count) <= CONV_STD_LOGIC_VECTOR(v_current_mod,LOG2M);
                                v_output_count := v_output_count + LOG2M;
                                
                                v_current_count := 1;
                            END IF;

following error occur::

 
Last edited by a moderator:

There is problems with these lines:

Code: 
output_stream(v_output_count+v_current_div-1 DOWNTO v_output_count) <= (OTHERS => '0');
output_stream(v_output_count+2-1 DOWNTO v_output_count) <= CONV_STD_LOGIC_VECTOR(v_current_mod,2);

If I replace with these lines;

Code: 
output_stream(5 DOWNTO 3) <= (OTHERS => '0');

No error reported.

Did you simulate the design before do the synthesis?

Thanks
 
hairo said:
There is problems with these lines:

Code: 
output_stream(v_output_count+v_current_div-1 DOWNTO v_output_count) <= (OTHERS => '0');
output_stream(v_output_count+2-1 DOWNTO v_output_count) <= CONV_STD_LOGIC_VECTOR(v_current_mod,2);

If I replace with these lines;

Code: 
output_stream(5 DOWNTO 3) <= (OTHERS => '0');

No error reported.

Did you simulate the design before do the synthesis?

Thanks
Click to expand...

yes i have simulated in xilinx ISE.
then why giving error in another line?
 

I dont know. I think there are problems with the variable values in the process block.
 

hairo said:
I dont know. I think there are problems with the variable values in the process block.
Click to expand...

actually i searched about this error in google but not much information...

what is this error that "constant value required"??

and when this error occurs??

if u know can u just tell me?
 

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