[SOLVED] synopsys design compiler error: mismatch signals width

[FvM]

I agree with hairo. A variable bit select is legal VHDL, a variable range select isn't. Although other compilers use to give better understandable error messages in similar cases, "constant value required" would refer to the requirement of a constant range in the expression mentioned by hairo.

A usual solution is a bit wise copy in a for loop.

 

[priyanka24]

I agree with hairo. A variable bit select is legal VHDL, a variable range select isn't. Although other compilers use to give better understandable error messages in similar cases, "constant value required" would refer to the requirement of a constant range in the expression mentioned by hairo.

A usual solution is a bit wise copy in a for loop.

but if i use for loop then its not synthesizable bcoz for loop is not synthesizable. if give me any suggestions to solve this error??

 

[soloktanjung]

For loop is synthesizable:

    process (clk)
    begin
        Count_Aux <= "000";
        for i in 0 to 10 loop
            if (a(i)= '0') then
                 Count_Aux <= Count_Aux + 1; -- operator "+" defined
                                             -- in std_logic_unsigned
            end if;
        end loop;
        Count <= Count_Aux;
    end process;

I synthesized in DC without error.

Thanks.

 

[priyanka24]

For loop is synthesizable:

    process (clk)
    begin
        Count_Aux <= "000";
        for i in 0 to 10 loop
            if (a(i)= '0') then
                 Count_Aux <= Count_Aux + 1; -- operator "+" defined
                                             -- in std_logic_unsigned
            end if;
        end loop;
        Count <= Count_Aux;
    end process;

I synthesized in DC without error.

Thanks.

but we used to hear that for loop is not synthesizable.
so any restriction or any kind of for loop is synthesized?

 

[soloktanjung]

From XST user guide:

The for statement is supported for:
• Constant bounds
• Stop test condition using any of the following operators:
– <
– <=
– >
– >=
• Next step computation falling within one of the following specifications:
– var = var + step
– var = var - step
where
♦ var is the loop variable
♦ step is a constant value
• Next and exit statements

 

[priyanka24]

From XST user guide:

but in my coding i want to check condition on whole binary number.

but in for loop once i got condition satisfied then it will come out of for loop.

and in my coding once condition is satisfied then have to perform some operation and after that want to return to next bit of my binary sequence. but how?

 

[FvM]

For loop is synthesizable

Yes, basically. Beginners often misunderstand HDL for loop as a sequence in time, similar to a C loop. That doesn't work, because a HDL for loop is a method to describe parallel logic. But there's a problem involved with the example:

The zero counting example doesn't work as most likely expected. According to VHDL rules, Count_Aux will only reflect the state of a(10) and ignore the other bits, because Count_Aux is only updated at the process end. You need to use a variable for different results.

A bitwise assignment of a signal, also with variable shift can be perfectly written as for loop, because the bits are independant of each other.

 

[soloktanjung]

The shown zero counting example however doesn't work as most likely expected. According to VHDL rules, Count_Aux will only reflect the state of a(10) and ignore the other bits, because Count_Aux is only updated at the process end. You need to use a variable for different results.

Yes that's true. I just want to prove that DC can synthesize VHDL for loop.

Thank you.

 

[priyanka24]

Yes that's true. I just want to prove that DC can synthesize VHDL for loop.

Thank you.

Hi Hairo..

as u said me removed that 2 lines which u said is having problem..

u r right both lines having problem.

after removing 2 lines my code got synthesized..

but now problem is that what should i do to replace both lines?

is there any technique to make that 2 lines synthesizable??

plz help me if you can

 

[FvM]

There's a little trick to overcome the limitation of a constant for loop iteration range:

FOR I IN INPUT_LENGTH-1 DOWNTO 0 LOOP
  IF (I <= v_output_count+v_current_div-1) AND (I >=  v_output_count) THEN
    output_stream(I) <= '0';
  END IF;
END LOOP;

Respectively:

temp_vect := CONV_STD_LOGIC_VECTOR(v_current_mod,2);
FOR I IN INPUT_LENGTH-1 DOWNTO 0 LOOP
  IF I = v_output_count THEN
    output_stream(I) <= temp_vect(0);
    output_stream(I+1) <= temp_vect(1);
  END IF;
END LOOP;

 

[priyanka24]

There's a little trick to overcome the limitation of a constant for loop iteration range:

FOR I IN INPUT_LENGTH-1 DOWNTO 0 LOOP
  IF (I <= v_output_count+v_current_div-1) AND (I >=  v_output_count) THEN
    output_stream(I) <= '0';
  END IF;
END LOOP;

Respectively:

temp_vect := CONV_STD_LOGIC_VECTOR(v_current_mod,2);
FOR I IN INPUT_LENGTH-1 DOWNTO 0 LOOP
  IF I = v_output_count THEN
    output_stream(I) <= temp_vect(0);
    output_stream(I+1) <= temp_vect(1);
  END IF;
END LOOP;

is there any alternative for " if " statement as me discussed with Hairo as found error in following lines::

output_stream(v_output_count+v_current_div-1 DOWNTO v_output_count) <= (OTHERS => '0');
output_stream(v_output_count+2-1 DOWNTO v_output_count) <= CONV_STD_LOGIC_VECTOR(v_current_mod,2);
output_stream(v_output_count+v_current_div-1 DOWNTO v_output_count) <= (OTHERS => '0');
output_stream(v_output_count+2-1 DOWNTO v_output_count) <= CONV_STD_LOGIC_VECTOR(v_current_mod,2);


so is there any alternative to make this lines synthesizable???

 

[priyanka24]

There's a little trick to overcome the limitation of a constant for loop iteration range:

FOR I IN INPUT_LENGTH-1 DOWNTO 0 LOOP
  IF (I <= v_output_count+v_current_div-1) AND (I >=  v_output_count) THEN
    output_stream(I) <= '0';
  END IF;
END LOOP;

Respectively:

temp_vect := CONV_STD_LOGIC_VECTOR(v_current_mod,2);
FOR I IN INPUT_LENGTH-1 DOWNTO 0 LOOP
  IF I = v_output_count THEN
    output_stream(I) <= temp_vect(0);
    output_stream(I+1) <= temp_vect(1);
  END IF;
END LOOP;

Hello FvM,

me not got this trick. can you plz explain me bit more.
also i have posted my part of code. according to Hairo said that lines are not synthesized which he posted.
can you help me to find trick to solve this problem. me facing problem in 4 lines and that lines are under "if" statement

 

[FvM]

I fear,you didn't read the suggested solutions thoroughly, or didn't understand the basic concept. The code with the if construct is in fact my suggested solution for the said two lines (no idea why you double posted them in post #31). There may be other solutions as well, but I'm not aware of it now and the posted solution obviously works.

Regarding the question, why is it done this way, please consider the conditions for synthesizable for loop staments as listed in post #25.

 

[priyanka24]

I fear,you didn't read the suggested solutions thoroughly, or didn't understand the basic concept. The code with the if construct is in fact my suggested solution for the said two lines (no idea why you double posted them in post #31). There may be other solutions as well, but I'm not aware of it now and the posted solution obviously works.

Regarding the question, why is it done this way, please consider the conditions for synthesizable for loop staments as listed in post #25.

yes later i got that this is solutions for my coding lines. but in this lines you said i have to declare another variable I?

 

[FvM]

but in this lines you said i have to declare another variable I?

The loop variable don't need to be declared in VHDL. But you need to add:

variable temp_vect: std_logic_vect(1 downto 0);

 

[priyanka24]

The loop variable don't need to be declared in VHDL. But you need to add:

variable temp_vect: std_logic_vect(1 downto 0);

Hi FvM,

i replaced those lines with your suggested trick and tried to synthesize it first in XILINX but me getting following error:

ERROR:Xst:787 - "E:/priyanka/Project/xilinx/trial/golombcoding.vhd" line 98: Index value <9> is not in Range of array <output_stream>.

what is problem can help me out?

 

[FvM]

Adjust the range for the respective loop

FOR I IN INPUT_LENGTH-2 DOWNTO 0 LOOP

 

[priyanka24]

Adjust the range for the respective loop

FOR I IN INPUT_LENGTH-2 DOWNTO 0 LOOP

why changed to subtraction parameter to '2' but.

will it affect my logic implemented by my code??

 

[FvM]

The problem is this:

The synthesis tools isn't able to determine the value range of v_output_count and similar variables at compile time. By using a for loop for the index, you can assure that only valid indices are used, despite of the actual values of v_output_count.

Your original code relies on the assumption, that in the expression output_stream(v_output_count+2-1 DOWNTO v_output_count) the selected slice is within the bounds of output_stream. If this assumption is correct, you can (and must) use the corrected loop range INPUT_LENGTH-2 DOWNTO 0 for the second loop construct.