try this command "set verilogout_no_tri true"
NAME
verilogout_no_tri
Declares three-state nets as Verilog
"wire" instead of "tri." This variable
is useful in eliminating "assign"
primitives and "tran" gates in the
Verilog output.
the variable "verilogout_equation"
NAME
verilogout_equation
Writes Verilog "assign" statements
(Boolean equations) for combinational
gates, rather than gate instantiations.
TYPE
Boolean
DEFAULT
false
This variable default status is false, so we need not to set it.
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