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synopsys DC synthesis problem

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qlmei

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synthesis assign

Hi all,

There is always "assign" statement in my verilog netlist after synthesis. I tried the following command before compile but it doesn't help. Please advise.

set_fix_multiple_port_nets -all -buffer_constants
set_simple_compile_mode true
set hdlin_keep_signal_name none.
 

no_mad

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verilogout_equation

Hi,

before you write out verilog netlist
and add

change_name -hier -rule verilog

to give better naming in netlist

Hope it helps
-no_mad
 

Thinkie

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set_fix_multiple_port_nets

With us, there are still some assigns left even with these option and we have a small perl script that fixes the netlist.
 

shiv_emf

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assign statements in netlist

assign r combinational statements .. whts the problem ??
why r u left with assign ??/
 

dcreddy1980

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synopsys dc synthesis tran

u can als try :

set verilogout_no_tri true
set verilogout_equation false
 

matthew_wang

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assign dc synopsys

Please go to synopsys, solvenet.com, I think you can get solution quickly.
 

sumit_techkgp

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verilogout_no_tri three state nets

PAR tool can take assign statements
 

straw

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synopsys verilogout_no_tri

if there is :
assign a=b
it's no problem
if it is a=c&b;
it need debug the script
 

quan228228

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verilog netlist assign

I also care this issue.
Every time we synthesis code, we always check assignment statement in netlist.

Does anyone has a good solution?


quan228228
 

sameer_dlh25

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assign +synopsys dc

Hi Qlmei,

I think set_fix_multiple_port_nets -all -buffer_constants should work. If it is not working than I have two suspects.

1. May be assign statements are not appearing in top design (Or what ever current design is set during compile). To prevent this you need to design names as well with the above command.

2. I hope you are giving above command before compile itself...:!:
 

deh_fuhrer

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synopsys dc assign

search for this article in solvnet they have provided a good solution to do that..
 

sumit_techkgp

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set verilogout_no_tri

Hello,
Even if you have some assign statements that should not be a problem as all backend tools nowadays accepts assign statements.
Sumit
 

shiv_emf

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assign statement in verilog netlist

assign statement in netlist ..it means some code is not synthesiable ?
plz explain
Shiv
 

shiv_emf

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i got it now ..
there is some synthesis variable .........
verilogequation which is set to false by default...
check the value of this variable
Shiv
 

quan228228

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try this command "set verilogout_no_tri true"

NAME
verilogout_no_tri
Declares three-state nets as Verilog
"wire" instead of "tri." This variable
is useful in eliminating "assign"
primitives and "tran" gates in the
Verilog output.

the variable "verilogout_equation"
NAME
verilogout_equation
Writes Verilog "assign" statements
(Boolean equations) for combinational
gates, rather than gate instantiations.

TYPE
Boolean

DEFAULT
false

This variable default status is false, so we need not to set it.


quan228228
 

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