Right, I think whoever synthesized the circuit in Cadence used the .lib file, but I'm now trying to use this Cadence synthesized code with the Synopsys tools I have because I am unfamiliar with Cadence. The person provided the library in Verilog code so that the definitions of the modules that Cadence uses are available. I'm just having trouble getting the user defined primitives into the library that the Design Compiler is looking at. There are definitions of modules that define all the ands and ors used, and by analyzing the lib/GSCLib_3.0.v file those definitions can be used in the uart_scan.v file in the Design Compiler. For some reason, unlike the modules in GSCLib_3.0.v, the user defined primitives are not being added as designs to the library so that they can be found while elaborating uart_scan.v.