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Synopsys DC Library Question

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sampham04

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Hi,

In Synopsys DC I tried analyzing and elaborating two files I have like this:

analyze -f verilog lib/GSCLib_3.0.v
analyze -f verilog src-Trojan-free/uart_scan.v
elaborate uart

but I get the following warnings:
Information: Building the design 'udp_mux2'. (HDL-193)
Warning: Cannot find the design 'udp_mux2' in the library 'WORK'. (LBR-1)
Information: Building the design 'udp_dff'. (HDL-193)
Warning: Cannot find the design 'udp_dff' in the library 'WORK'. (LBR-1)
Warning: Design 'uart' has '3' unresolved references. For more detailed information, use the "link" command. (UID-341)

I know that udp_mux2 and udp_dff are primitives in lib/GSCLib_3.0.v so I don't understand why they cannot be found. Should I be analyzing the file differently? Or is this a warning that I can just ignore?

Thanks!
 
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kornukhin

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Library primitives (AND, OR, NOT, DFF...) should be in Liberty (.lib) format.
I think you need:
- set GSCLib_3.0.lib as link_library
- don't analyze GSCLib_3.0.v
 

sampham04

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The reason I have to analyze the GSCLib_3.0.v file is because the uart_scan.v file that I have was synthesized in Cadence. All the library primitives that Cadence uses are in the GSCLib_3.0.v file. Using this file the normal (and, or, not, dff...) primitives that are used in the uart_scan.v file can be found except for the udp's that I mentioned earlier.
 

kornukhin

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RTL Compiler (from Cadence) also needs .lib file to synthesize.
 

sampham04

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Right, I think whoever synthesized the circuit in Cadence used the .lib file, but I'm now trying to use this Cadence synthesized code with the Synopsys tools I have because I am unfamiliar with Cadence. The person provided the library in Verilog code so that the definitions of the modules that Cadence uses are available. I'm just having trouble getting the user defined primitives into the library that the Design Compiler is looking at. There are definitions of modules that define all the ands and ors used, and by analyzing the lib/GSCLib_3.0.v file those definitions can be used in the uart_scan.v file in the Design Compiler. For some reason, unlike the modules in GSCLib_3.0.v, the user defined primitives are not being added as designs to the library so that they can be found while elaborating uart_scan.v.
 

kornukhin

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I understand your problem, but DC needs timing and functional information from .lib. Even if you somehow find udp_mux2/udp_dff verilog source code you can't synthesize your module or make timing analysis or power analysis using DC. Verilog files doesn't contain all necessary information.
Try to find GSCLib.lib inside Cadence install directory.
 

wsong0210

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make sure your search paths have *
Here * means all design libraries you have analysed.
 

sampham04

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So, if I find that .lib file with the time and power analysis information then I just include that into the library and it will work? Would I just analyze it to include it to the library or do I need to use another command?

I have a .sdf file that has timing information, but I think that the link_library will only take .db files.
 
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kornukhin

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To create .db file you need:
1. Open DC
2. read_lib gsclib.lib
3. write_lib gsclib -o gsclib.db

To use it
set target_library gsclib.db
set link_library { * gsclib.db }
 

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