lagoule
Newbie
Hello,
In a design for a class (a bad design IMHO, but I have to deal with it...), a chip access an external asynchronous memory.
Therefore, there is a path from the transition of addr rd/wr signals to the output pads to the async memory to the input_pad to the input registers in my chip. My problem is how to tell synopsys about that path?
When compiling the design, synopsys closes the timing from the internal signals to the output pads (according to the clock). It also closes the timing from the input pads to the internal registers. I just can't figure out how to tell it that both are related.
Thanks you,
Jonathan
In a design for a class (a bad design IMHO, but I have to deal with it...), a chip access an external asynchronous memory.
Therefore, there is a path from the transition of addr rd/wr signals to the output pads to the async memory to the input_pad to the input registers in my chip. My problem is how to tell synopsys about that path?
When compiling the design, synopsys closes the timing from the internal signals to the output pads (according to the clock). It also closes the timing from the input pads to the internal registers. I just can't figure out how to tell it that both are related.
Thanks you,
Jonathan