Synopsys & Cadence tutorial

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Hi ,
cananyone pass me the information on DC and RTL complier

Thanks

Added after 12 minutes:



Hi ,
cananyone pass me the information on DC and RTL complier

Thanks
 

the best language to learn is verilog
 

what s0shinde said is very good,i am using some of these tools too,come on.
 

Hi,
well in ASIC designing it's healthy job doing any thing just by knowing MAGIC and B-Spice

in ASIC design taking EDIF netlist into consideration everything follows for a pertyicular design

Added after 38 seconds:

Hi,
well in ASIC designing it's healthy job doing any thing just by knowing MAGIC and B-Spice

in ASIC design taking EDIF netlist into consideration everything follows for a pertyicular design
 

practice users_guide for all you need.
 

could u explain why the (3) can fix setup violation please?

 

who know???javascript:emoticon(':?:')
Question
:?::?::?::?:
 

ya the last option which you told is pretty common n very easy to do. its called as pipelining. you just try dividing your combinational logic n place a flip flop in between to meet the timing. just inform me whatever happens. bye



Added after 4 minutes:

hi does anybody have the synopsis DC, n cadence reference material for RTL design n simulation??? i know Xilinx ISE n EDK but want exposure to more tools...
 

hi guys. does anybody know how should i start my job search in the vlsi, asic industry. i have a good hand on FPGAs. ie verilog vhdl.....rtl design....etc.
 

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