Concise tutorial about how to run Synopsys tools from RTL to GDS?

[unixdaemon]

I am mostly a software person, but I can program in Verilog and I understand the ASIC design workflow in general.
Through my job I have access to all Synopsys tool licenses.

Is there a concise tutorial that describes step by step how to run Synopsys tools to build GDS from Verilog? Alternatively, a set of shell scripts that do the same would be helpful.

I am not after production quality of results. My purpose is to learn how to run the tools at the command line level.

 

[oratie]

If you have access to solvnet, you may download RM (reference methodoloty) set of RTL-to-GDS scripts. (it is also avaialable in the ICC2/FC GUI Help menu)

Overview
========
This RM script package contains scripts to run a full RTL to GDSII flow. You can run
from synthesis through the entire place and route flow with these scripts.

 

[unixdaemon]

There are several reference methodology downloads on solvnet that have the word 'compiler' in them: Design Compiler, Fusion Compiler, IC Compiler, IC Compiler II.

Are all of them able to compile from RTL to GDS? What is the difference between them?

 

[oratie]

Well, Fusion Compiler = DC + ICC (ICC2). So, if you have access to Fusion Compiler - it is the best choise,

 

[unixdaemon]

@oratie

I tried to run FC-RM_U-2022.12 but it fails to run simple Verilog modules. It fails with errors like:

RM-error: Design has no site rows or site arrays. Please fix it before you continue!
RM-error: Design has no signal terminals. Please fix it before you continue!
RM-error: Design has no tracks. Please fix it before you continue!
RM-warning: Design does not contain any PG shapes. You do not have proper PG structure. If this is unexpected, please double check before you continue!
RM-warning: Design has no boundary or tap cells. If this is unexpected, please double check before you continue!

Do you know what is the minimal tcl script that can compile a simple Verilog module to GDSII?

 

[dpaul]

Synopsys RMs or UGs from Solvnet would be the most authentic sources. If you have access to the tools, you or someone else in your org must have a Solvnet login.

 

[unixdaemon]

@dpaul

I have the SolvNet login, but FC RM breaks, see my last message above.

 

[rca]

If you know the ASIC word, as you mentioned , you understand the row is not define and the tool cannot place any std cell...

Read the documentation and start by doing a simple synthesis to then place this netlist... and the following steps.