Synopsys & Cadence tutorial

[s_vlsi]

Hi ,
cananyone pass me the information on DC and RTL complier

Thanks

Added after 12 minutes:



Hi ,
cananyone pass me the information on DC and RTL complier

Thanks

 

[straw]

the best language to learn is verilog

 

[sevid]

what s0shinde said is very good,i am using some of these tools too,come on.

 

[sekartut]

I have the tanner tutorial.
You need
respond my reply.

Sekartut

 

[Ramesh Reddy]

Hi,
well in ASIC designing it's healthy job doing any thing just by knowing MAGIC and B-Spice

in ASIC design taking EDIF netlist into consideration everything follows for a pertyicular design

Added after 38 seconds:

Hi,
well in ASIC designing it's healthy job doing any thing just by knowing MAGIC and B-Spice

in ASIC design taking EDIF netlist into consideration everything follows for a pertyicular design

 

[eivala]

see http://www.ece.uic.edu/consulting/using/synopsys.html

http://www.polybus.com/hdlmaker/users_guide/

 

[liu_uestc]

good!

 

[xiexie57]

practice users_guide for all you need.

 

[littlefield]

could u explain why the (3) can fix setup violation please?

Hello,
I have a question to ask.
Suppose there are two flipflops in an ASIC design and there is Some combinatorial logic between them. Now there is a setup time violation in the second flipflop. How can we correct this setup time violation? I know of some techniques, can anyone suggest some more. If anyone knows how to do that in Synopsys DC or Primetime, any commands. Also correct me if I am wrong

(1) Modify the combinatorial logic is one way. But suppose it is not possible to reduce to more.
(2) Use of larger sized gates in that combinatorial logic.
(3) Replace the first flipflop with 2 transperant latches connected in Master-Slave mode.
(4) Divide the Combinatorial path in to two and place a flipflop between them.

Are these correct. Any sugestions.

 

[littlefield]

who know???javascript:emoticon(':?:')
Question

could u explain why the (3) can fix setup violation please?

Hello,
I have a question to ask.
Suppose there are two flipflops in an ASIC design and there is Some combinatorial logic between them. Now there is a setup time violation in the second flipflop. How can we correct this setup time violation? I know of some techniques, can anyone suggest some more. If anyone knows how to do that in Synopsys DC or Primetime, any commands. Also correct me if I am wrong

(1) Modify the combinatorial logic is one way. But suppose it is not possible to reduce to more.
(2) Use of larger sized gates in that combinatorial logic.
(3) Replace the first flipflop with 2 transperant latches connected in Master-Slave mode.
(4) Divide the Combinatorial path in to two and place a flipflop between them.

Are these correct. Any sugestions.

:?::?::?::?:

 

[rohiteda]

ya the last option which you told is pretty common n very easy to do. its called as pipelining. you just try dividing your combinational logic n place a flip flop in between to meet the timing. just inform me whatever happens. bye

Hello,
I have a question to ask.
Suppose there are two flipflops in an ASIC design and there is Some combinatorial logic between them. Now there is a setup time violation in the second flipflop. How can we correct this setup time violation? I know of some techniques, can anyone suggest some more. If anyone knows how to do that in Synopsys DC or Primetime, any commands. Also correct me if I am wrong

(1) Modify the combinatorial logic is one way. But suppose it is not possible to reduce to more.
(2) Use of larger sized gates in that combinatorial logic.
(3) Replace the first flipflop with 2 transperant latches connected in Master-Slave mode.
(4) Divide the Combinatorial path in to two and place a flipflop between them.

Are these correct. Any sugestions.

Added after 4 minutes:

hi does anybody have the synopsis DC, n cadence reference material for RTL design n simulation??? i know Xilinx ISE n EDK but want exposure to more tools...

 

[rohiteda]

hi guys. does anybody know how should i start my job search in the vlsi, asic industry. i have a good hand on FPGAs. ie verilog vhdl.....rtl design....etc.