structured asic design tools

[BoTig]

Hi all,

I just looked into easic.com and found there design flow picture.
In that picture is shown that it is posible to make sinthesis using Magma or Synopsys. After synthesis next step is placement and optimization. But only Magma is shown there.

If someone has experienc in structured ASIC design flow tools please let me know is it posible to design only using Synopsys tools?

Thank you very much.

 

[msaadrahman]

Hi,

I assume you mean a RTL-> GDSII flow. In that case you need Modelsim to write your code in VHDL, for synthesis you can use Synopsys tools which will map the libraries according to the process that you are going to use for the chip tapeout. After Synthesis the tool will generate a .v file which you will import in a Place and Route Tool such as SoC Encounter. In SoC Encounter you can do the Pad Frame or otherwise import the gds file in Cadence Virtuoso and connect it with some analog part in your design or do the pad frames in Virtuoso. After that you stream out the design in a gds2 format.

If I have missed the question or if anything is not clear than please restructure your query.

-Saad Rahman

 

[BoTig]

I forgot to mention that I'm interested in structured asic design tools.
As I understand I can use DC for sinthesis but after synthesis and before etools I need also 1 step (I thing this should be some kind of placement). And I dont know which tools can I use in this step?