lhlbluesky
Banned
i have designed a sc-opamp, as fig1 shows (op1.jpg).
Cs/Cf=5/6, Vrefp-Vrefn=0.9, and (Vin+)-(Vin-)=0~1.8,
so (Vout+)-(Vout-)=-0.75~0.75;
and the timing as fig2 shows (timing.jpg).
fig3 (op2.jpg) is the OTA schematic, C1 C2 are the compensation capaciotr.
when post-simulation, i found that, the output voltage resolution decreases with the amplitude of input voltage, that is, when ((Vin+)-(Vin-))-((Vref+)-(Vref-)) is larger (600mv or more), the output voltage ((Vout+)-(Vout-))resolution can reach 12bit or more, however, when ((Vin+)-(Vin-))-((Vref+)-(Vref-)) is smaller (100mv or less), the output voltage ((Vout+)-(Vout-))resolution decreases a lot (to 9bit or less). it is very strange. (calibre R+C+CC)
when i extract capacitor only (C+CC), the resolution has no decrease with input voltage, but when i extract resistor only (R), the resolution decreases with input voltage.
besides, when i extract netlist only for OTA, the same case occurs (when i extract capacitor only (C+CC), the resolution has no decrease with input voltage, but when i extract resistor only (R), the resolution decreases with input voltage), that is, it is the parasitic resistor in OTA that causes this problem. but why? how can i find the destructive parasitic resistor? i'm really confused. pls help me.
besides, i want to decrease the parasitic capacitor in X and Y node (in layout), that is, i want to decrease the parasitic capacitor of top plate of Cs relative to ground (or Cs top plate to node '0'), then, what methods can i use?
pls help me. thanks in advance. thanks all.
Cs/Cf=5/6, Vrefp-Vrefn=0.9, and (Vin+)-(Vin-)=0~1.8,
so (Vout+)-(Vout-)=-0.75~0.75;
and the timing as fig2 shows (timing.jpg).
fig3 (op2.jpg) is the OTA schematic, C1 C2 are the compensation capaciotr.
when post-simulation, i found that, the output voltage resolution decreases with the amplitude of input voltage, that is, when ((Vin+)-(Vin-))-((Vref+)-(Vref-)) is larger (600mv or more), the output voltage ((Vout+)-(Vout-))resolution can reach 12bit or more, however, when ((Vin+)-(Vin-))-((Vref+)-(Vref-)) is smaller (100mv or less), the output voltage ((Vout+)-(Vout-))resolution decreases a lot (to 9bit or less). it is very strange. (calibre R+C+CC)
when i extract capacitor only (C+CC), the resolution has no decrease with input voltage, but when i extract resistor only (R), the resolution decreases with input voltage.
besides, when i extract netlist only for OTA, the same case occurs (when i extract capacitor only (C+CC), the resolution has no decrease with input voltage, but when i extract resistor only (R), the resolution decreases with input voltage), that is, it is the parasitic resistor in OTA that causes this problem. but why? how can i find the destructive parasitic resistor? i'm really confused. pls help me.
besides, i want to decrease the parasitic capacitor in X and Y node (in layout), that is, i want to decrease the parasitic capacitor of top plate of Cs relative to ground (or Cs top plate to node '0'), then, what methods can i use?
pls help me. thanks in advance. thanks all.
