[SOLVED] Strange mismatch between layout & schematics (AMS 0.35 HV)

[K4R1]

Hello,

Routing some nmos20t in 0,35 HV, i got a very strange parameters mismatch between the layout and schematic, where there should be none. My LVS error report tells me that their is a mismatch of 20% which is completely impossible since the schematic transistor and layout transistor have the same parameter. I'm enclosing a screenshot to picture the problem, if anyone can help me please !!!



the twisted thing is that i have re-imported the layout of this MOS to make sure it has been correctly "translated" and i also already layouted a same mos before with no problem... But this time, it seems to not be happy.

K4R1

 

[lamoun]

Hello,

Fix the net errors first.
Sometimes wiring errors affect transistor parameters.

 

[K4R1]

Ok, I'm looking at it right now... Besides, what's the purpose of the "psub" pin ? Where it should go ? It seems to make me short cut wherever i pin it....

Thanks for your time

 

[K4R1]

Ok, i solved it... It was very tricky but obvious. You can't pin "mosN20t" with "mosi20t" !!

So to fix this, i simply separated the bulk polarization and joined them where it was needed. Have a glance at the image enclosed to the message...