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[SOLVED] Pin Order Mismatch Between Quantus QRC Extracted Netlist and Maestro Subcircuit Instantiation

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m.m.m

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Hi everyone,

I’ve run into an issue with my design when using Quantus QRC (Assura) for parasitic extraction and simulating the design in Cadence Virtuoso with Maestro.

After running Quantus QRC on my layout, it generated a SPICE netlist for the extracted view. However, I’ve noticed that the pin order in the subcircuit within this SPICE netlist is different from the pin order used when Maestro instantiates the same subcircuit during simulation. As a result, my design doesn’t function properly in the simulation.

Here's the instance in the schematic view:
1726495904683.png

and the created netlist for simulation:
1726495853448.png
(net5 is connected to OUTB.)
But the extracted hspice subckt has the following port config:
1726495860475.png

And the layout pins have the same names and labels as the ones in schematic, and LVS gives no errors.
1726496124908.png


I can manually reorder the subckt pin order in the netlist but it would be rewritten each time I extract the netlist, which is not ideal at all.
So I'd appreciate your suggestions.
 

Hi @m.m.m ,
The first idea that comes into my mind is that you must have changed your symbol manually after modifying the schematic which may have led to the problems in pin order. You can try to open your schematic view, do Check and Save and after that go to Create -> Cellview -> From cellview and in pop-up menu click "modify". It should suggest you to update the CDF order as well and after that the port order should be fixed.
Alternatively, you might go to (in CIW): Tools -> CDF -> Edit.. and fix it directly from CDF manager.
Hopefully, that helps.
 

To my understand
Assura was used to generate SVDB.
Quantus to generate extracted view.
Questions:
1. What is the type of extracted view which was generated (selected QRC output)?
2. Does issue occurs for different output types?
3. Is CDF consistent with netlist?
 

Hi @m.m.m ,
The first idea that comes into my mind is that you must have changed your symbol manually after modifying the schematic which may have led to the problems in pin order. You can try to open your schematic view, do Check and Save and after that go to Create -> Cellview -> From cellview and in pop-up menu click "modify". It should suggest you to update the CDF order as well and after that the port order should be fixed.
Alternatively, you might go to (in CIW): Tools -> CDF -> Edit.. and fix it directly from CDF manager.
Hopefully, that helps.
Thank you, However recreating the cellview symbol didn't fix it either.

To my understand
Assura was used to generate SVDB.
Quantus to generate extracted view.
Questions:
1. What is the type of extracted view which was generated (selected QRC output)?
2. Does issue occurs for different output types?
3. Is CDF consistent with netlist?
Thank you Dominik for your response,
I'm extracting Spice output from QRC.
1726500210877.png

I tried the Dspf type and it had the same problem.
I haven't had experience with reading/configuring the CDF. Could you please tell me what I should be looking for? I couldn't find a proper tutorial.
--- Updated ---

I switched the netlist extraction option to av_extracted. now the problem is changed 😐
the instance in the netlist has an extra VDD pin for some reason. But this time the port order is correct at least.
instantiation:
1726507030349.png

subckt definition:
1726507038117.png
 
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