Standby Mode: Analog Circuit

[sachinagg77]

check circuit floating node

What means should be adopted to identify all possible cause of leakage during the standby mode for an analog circuit?

What should be done to ensure that there is no leakage current during the standby mode?

With Regards
Sachin

 

[szekit]

analogue sleep mode cct

leakage through the gate of a big transistor?

leakage through any switches (standard cell) when they are off. try to increase the channel length or stack the devices in series.

any forward bias junction diodes?

 

[gafsos]

Hi,
Enjoy it
gafsos

 

[sachinagg77]

Thanks for the responses. I am sorry but I was unable to put my question properly.

I had a problem with one of my circuits. The circuit had an unused inverter (spare). This inverter was connected to power supplies but its input and output were floating. Simulations to check the standby (power down) mode showed no leakage as the simulator set the inverter input automatically to VDD. By in the actual test chip, there was a leakage of around 100uA through this inverter.

Could anyone please let me know how to identify such mistakes (such as open inputs to digital gates) during simulation?

With Regards
Sachin Aggarwal

 

[jcpu]

Dear Sir,

Indeed, simulators won't be able to check floating digital input.
But real chip shall give you leakage for sure by emission picture.

Only way off my head is in Cadence Compsor,
unconnected input pin shall receive a warning messge.

have fun,

 

[sachinagg77]

Dear JCPU

Thanks for your response. As you mentioned, I too presently depend on visual inspection based on Cadence warnings. I think the visual inspection works fine with small circuits but there are chances of errors for large circuits. Cadence issues warnings for many other reasons too and a designer may occasionally fail to identify a valid warning point.

Any ways, please do inform me if you are able to find any other method to identify such problems.

With Regards
Sachin Aggarwal

 

[rfsystem]

The issue which hurt most standby or controlled power off analog circuits are

1. Static floating gates
2. Dynamic startup conditions

The "floating gates" is derived from typical logic application where dynmaic logic is used and there exist a logic combination which lead to a floating node. Because the operating clock could be much lower than the maximum clock there is the chance that the leakage current combination of technology different diodes, e.g. P+NWELL and N+PSUB, lead to an unknow voltage at this node. If this node drive a logic state the state becomes unknown.

A similar situation could exist in power off switched analog circuits; one node gets floating and there is a connected gate which could pass current from VDD to VSS. I have studied in the early 90s an automated floating gate check method based on netlist inspection and .OP analysis results from Spice.



There are also some other tricks. One of these is to run 2 .OP analysis. The first where the P+NWELL diodes have leakage x100 and the other is where N+PSUB have x100 or other factors. Then all nodes are checked for critical voltage change. I have done that with scripts. But it only identifies critical nodes which are floating which is a warning but does not lead nessecary to a leakage path.

In effect a modified Spice should be able to print the impedance of every node to node "zero" but the development of the kernel stopped about 20 years ago.

I have collected so many missing links in the analog design automation that it is time to give them an audience.

 

[hung_wai_ming@hotmail.com]

To check floating nodes, there are some ways I know
(1) Visual inspection
(2) Caden*e compos*r with floating nodes flagging
(3) Nanos*m with simulation output showing ALL floating nodes

Presently, we are using (1) and (3) to check it. However, whenever there are floating nodes, H*pice should be able to check it and display currents.

I think as a analog designer, always one should notice that there is leakage current when drain/source not equal or gate node is have voltage biased to turn-on state, so in practice, you should always have transistors to tie ALL working transistors to either ground or VDD when in sleep mode or standby node. I have seen this mistake from many graduates from school that they have no knowledge to deal with leakage since in research there is no need to concern about leakage. Only in commercial area, we concern leakage.