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Flat top PAM. Analyze the trace below. What do you see?
1. Sine wave sample & hold at least 6 times per cycle. It could be more or less but the result may change.
2. A 50 % duty factor of 0V and held sample
So you need a sine gen, a sampler square wave at some variable speed say 6x , a sample & hold and a SPDT analog (MUX) switch and then coordinate the logical tasks of each component into a schematic.
Now go do your homework.
I did not bother to find a better picture than above. Forgive me but the "flat top" sample of the sine wave should "hold" at a pre-defined instant relative to the clock, such as leading edge and not wander to the trailing edge.
I'm reminded of digitized audio. Read voltage of the incoming waveform. Convert the analog value to binary. Usually it's done several thousand times per second.
A stiff-enough buffer amp and a switch, after whatever sets the level.
"Stiff enough" is either by open-loop-sizing, or by an outer loop that
trues up the buffer "quick enough" after the edge soaks up load
dV/dt current and sags it.
Here's one way using CMOS unipolar , I just tried.
This is an alternate Track & Hold method onto two caps at 1/2 the PAM rate then stores the values with a small RC delay of the 2nd SPDT CMOS switch then finally multiplexed with ground on the 3rd switch. A divide by 2 FF creates the sample clock while the input clock alternates between 0V and the tophat S&H voltage. There are simpler ways low RdsOn and narrow Sample pulse. Never use ceramic for your hold capacitor to avoid voltage sensitive capacitance that causes hysteresis.
Metal film caps are a good choice.
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