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analog pulse shaping strategy question

yefj

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Hello i need to convert a 0-3.3V 120ns 500ns period pulse into -2v to -5V pulse to turn on and off CGHV1A250F.
I got the circuit shown below ,but its very odd.
I need to control the upper level lower level and keep the output pulse as square as possible.
Is there some new circuit configuration you could reccomend me to use instead the circuit i got?
Thansks.




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I would go with a grounded-base PNP, emitter resistor
to the 0-3.3V pulse source and a collector resistor to -5V.
Co-scale the emitter and collector 1:1 and you'll be
roughly right, tweak to accommodate the V3p3-Vbe error.
 
Agreed regarding preceding post. You can apply positive bias pulses directly to the base of the PNP. No need for capacitor blocking. The PNP can take power from a negative rail. Expect to do a lot of adjusting to yield your desired volt levels.
 
@yefj you should be aware that B-E junctions in reverse will zener and pass current if they get to ~ 6V reverse, varies for different transistors - read the data sheet !
 
Hello ,The issue with such circuits that in order to pass the pulse i need to use transistors with as higher bandwidth as possible.
What higher BW BJT you could reccomend me to improve the shape of the output ?
Thanks.

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Hello, Macom company answered my question as shown below the astrix.
I dont understant this answer, in the end of my circuit there is a load which is supposed to represent CGH1A250F.
I know to know how to represent it some how.
How exactly do i suppose to interpret this answer into a simple R or C model of the load?

*************************************
"The gate capacitance you refer to below is the absolute maximum for the part.
In real operation you should never see this value.
Here is a snapshot of the gatecurrent vs. drive-up & freq.

You may see up to 2mA if operating in saturation and depending on the frequency.

This is the typ. Max stated in the DS, you may design your circuit with a little headroom for tolerances. It is also a question if you drive the device that much into saturation."

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"As square as possible" is a function of budget, schedule and clue.
That seems not-promising and endless.

You should pause right now and quantify, or you will just chase
the white whale indefinitely (and then declare "good enough"
anyhow, once you get up against the deadline).

Might start with how you plan to "control" output VOH, VOL.
One is evidently a fixed supply and one is an analog outcome.
But also see softness about that. If you want sharp then you
need low Cstray and low Zout. If your -2V was also a supply
then you could put LVC single gate logic parts at front and
back with only a level shift between.

For that matter are you certain there is no part out there that
does this, good-to-go? Because there -are- families of logic
level shifters. Whether your application (which looks like it's
"whatever, today") provides what they need, or could be
modified to do so, is another question.
 
Hello dick_freebird,You say maybe what i was so far doing is good enogh.
for the gate I get -2 to -5 and current of 30mA on the 200Pf a consider the load.

From the drain biasing side i have another circuit which i assume 45/15A= 3ohm resistor is my load as depicted from the data sheet.

I dont have a model , So i am doing my best with what i can using the datasheet.
Suppose i will build a PCB combining these two circuits and i plug the transisor to the system.
What wil happen?
Thanks.
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