analog logic of driver circuit

[yefj]

Hello , I was given the following driver.
given the circuit and the result below, what is the analog logic for the BW and gain of in the circuit below?
LTspice file is attached.
Thanks.

 

[barry]

i don’t know what “analog logic” is.

 

[D.A.(Tony)Stewart]

Differential VCCS

The logic diagram (aka schematic) indicates a differential voltage input with common mode rejection with single-ended voltage feedback and differential current sense feedback.

Rather than use a +/- input for differential feedback, it uses the inverted output from the other Op Amp using the inverted input for feedback. (double negative= +Vref)

But the current sense R8, R9 was chosen larger than the local NFB from R2, R4 to avoid an open loop gain situation if the load opens causing both outputs to saturate from input offset.


I am not familiar with the optimal choices for voltage and current gain .

I might have changed R1 from 226 to 374.5 and change R8, R9 to match R2,R4 = 1k5 giving 1mA per mV input with Rs = 10

 

[yefj]

Hello Tony,I want the create the situation you described.how do I test open loop gain in this circuit ?
So I could see the saturation you described.
"But the current sense R8, R9 was chosen larger than the local NFB from R2, R4 to avoid an open loop gain situation if the load opens causing both outputs to saturate from input offset."

 

[D.A.(Tony)Stewart]

This looks like open loop gain but zero input offset in a small signal transfer function but not quite.

I guess you can figure out how to do the Transient test.

 

[yefj]

how can i test the feedback in time domain .
I want to see the current sensing and feedback in time domain.