wsad520wsad
Newbie
Recently, I study about current mode logic(CML) v.s charge steering logic(CSL).
So, I found paper "Charge Steering: A Low-Power Design Paradigm"[1],
and the paper is compare CML to CSL power,
there is thing so confuse me,
why CML circuit must provide a bandwidth of about 0.7rb, where rb is operation rate.
[1] B. Razavi, "Charge steering: A low-power design paradigm," Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, San Jose, CA, USA, 2013, pp. 1-8, doi: 10.1109/CICC.2013.6658443.
So, I found paper "Charge Steering: A Low-Power Design Paradigm"[1],
and the paper is compare CML to CSL power,
there is thing so confuse me,
why CML circuit must provide a bandwidth of about 0.7rb, where rb is operation rate.
[1] B. Razavi, "Charge steering: A low-power design paradigm," Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, San Jose, CA, USA, 2013, pp. 1-8, doi: 10.1109/CICC.2013.6658443.
