logic of a transistor circuit logic shown below

[yefj]

Hello , In the photo below, how do i know what is the analog design logic of the structure between the two arrows in the photo below?
Thanks.

 

[dick_freebird]

Looks like a PNP Darlington to me, just following the trim-pot
wiper voltage to make a buffered output from "whatever". No
logic per se.

 

[yefj]

Hello , yes I understand .it’s a circuit which passes there it a pulse .
Before the Darlington at point D I have a resistor R20 and Q1 what is the logic of that area?
Thanks .

 

[danadakk]

If D goes - with respect to ground during pulse Q1 conducts more. That in turn pulls Q3 Q4 bases more - with respect to
gnd and they conduct more so their emitters go more - and
hence so does D.

Q1 & (Q3 Q4) are a "darlington", Q3 Q4 simply paralleled transistors.

Logically the circuit is a buffer.....


Regards, Dana.

 

[yefj]

Hello Dana,I am trying to underatnd the logic of the stage before the buffer.
There are a lot of resistors and a PNP at point C.
We have some pulse going to PNP ant point C and R13 is some variable resistor which on one end goes into the get of Q1 while on the other its on the -8V power suplly.
What is the analog logic in that?
Thanks.

 

[danadakk]

R13 seems to be a trim of the pulse amplitude being fed to Q1.

So as pulse goes - into Q2 its collector goes more positive towards ground.
So it acts as an inverter.


Regards, Dana.

 

[yefj]

Hello Dana, I think that the first part from point A to point B is a level shifter.
I know that the reverse voltage of the zener is 3.6V ,what do you think is the input pulse i can use and what output pulse i will get at point B?

I could not find the BZT52C3V6 so i used 1N750 with 4.7 Breadown voltage instead of 3.6.
in the simulation bellow i see two things:
1.why i get distorted output signal in my simulation?
2.my level shiting is linked to the reverse breakdown voltage of the zenner.how does the zenner diode reverse breakdown impact the level shifting?
How this level shifting logic works?
Thanks.

 

[danadakk]

The peaking in the square wave due to the differentiator action of
C16 R16. Classic response.

What is RC Differentiator? Circuit Diagram, Working & Waveforms - ElectricalWorkbook

A RC differentiator circuit consists of a series combination of a capacitor C and a resistor R. The input signal is fed across the combination and output is obtained across the resistor.

electricalworkbook.com

This whole signal path is not really logic, its an analog signal path.

The zener I think clips the max differentiator peak, and causes a vdrop at DC
of the input signal.


Regards, Dana.

 

[yefj]

Hello Dana ,regarding the good observation you did:
in my point of view when Vi-Vout>Vbreak_down of zenner then the Zenner will open_up and make Vi=Vout.
but why exactly the zenner does offset drop? what is the analog machanism to that?
Thanks.
"The zener I think clips the max differentiator peak, and causes a vdrop at DC"

 

[danadakk]

When the zener conducts its V drop is fixed at its value, so any signal applied at input to it will appear
on otherside offset by its V. As you see below even though current thru it changes a lot its V stays
constant, quadrant 3 below.

Regards, Dana.

 

[dick_freebird]

Zener limits the charging of the input cap and the signal
passed to the peak detect and buffer; above zener knee
the input is wasted into the 550 ohm / 10nF / -2.5V bucket
making an input amplitude max of roughly 1V.

 

[danadakk]

Sim I get :

And input 6.6V and input Z taken out of the circuit :

Regards, Dana.

 

[yefj]

Hello, We have basickly a difertiator , which creates these peaks as shown on the photo without the diode.
reverse voltage is 3.3V forward voltage is 0.6V of the diode.

Vout at first is -2.5V so the diode will stop being forward biased at -1.9V, but our pulse is 0-3.3 so the diode will be always forward biased.What is the physical intuition on when the Zenner in in forward biased and when its in reverses biased?
Thanks.

 

[KlausST]

We have basickly a difertiator

I recommend to differentiate between
* (RC) high pass filter
* and a true differentiator

A HPF has a cut off frequency and thus causes this exponential output shape (the peak voltage depends on step voltage)
A true differentiator has no cut off frequency and thus causes a sharp, short output peak ( the peak depends on dV/dt)
In a bode plot you see the flat horizontal gain line of a HPF, which does not exist on a differentiator.

Some documents say that they are working similar ... but only when f_signal is much lower than f_c .. which isn´t the case here.
If f_signal is much lower than f_c then you don´t see the exponential shape at all.

Klaus

 

[danadakk]

Zener turn on occurs ~ +.6V, due to the prebias of 2.5V, note its a 3.6V model :

Odd the Zener is supposed to be 3.6V but actual seems to be 3.2, model issues ......and its dynamic R quite
low, << 1 ohm......go figure.....


Regards, Dana.

 

[KlausST]

Odd the Zener is supposed to be 3.6V but actual seems to be 3.2, model issues .

According datasheet, V_Z (3.6V) is measured @ I_Z of 60mA.
In the simulation I_Z goes up to 7mA only.
Tolerance of the "C" rated one is +/-0.2V.

r_diff accroding datasheet is 15 Ohms @ 60mA

****
I wonder how accurate the model is.

Klaus

 

[danadakk]

Model is screwy because 15 ohms at 60 mA is .9v, and sim does not support that.

Although at 60 mA 3.6V is close. Posit if one delved into device physics for that
specific geometry and process.....


Knight

 

[KlausST]

Model is screwy because 15 ohms at 60 mA is .9v,

it is "r = 15 Ohms", not "R = 15 Ohms"
* "R" denotes absolute resistance R = V / I, while
* "r" denotes differential resistance r = dV/dI

In the meaning if you rise the current by 10mA (like from 60mA to 70mA)
The voltage will rise about 10mA * 15 Ohms = 150mV (delta) (let´s say from 3.60V to 3.75V)

Don´t know how good the model is in this regard. I´m not very experienced with simulations at all.

Klaus

 

[danadakk]

Actually if we let dI get very small, hence dV follows, we approach R in the limit.

The zener guys liken their slope to an impedance, which is a complex value, but no freq specified.
But then if you look online the definition of impedance it varies from AC to AC or DC. Rigor-less
machinations of our profession.

Knight

 

[D.A.(Tony)Stewart]

I am trying to analyze the missing fundamental knowledge in your questions to help you improve your focus. Perhaps some is due to ESL which is not parasitic inductance but English Second Language and partly lack of experience.

Logic is based on assumptions and reasoning with thresholds and tolerances. This applies to TTL/CMOS and human logic, yet it does NOT apply to ANALOG DESIGN. (even though all TTL/CMOS Logic design is also ANALOG)

If you have transistor design 101 training, we assume you understand without explanation all the analog characteristics of Common Emitter (CE) , CC and CB, but allow some reminders. Your questions often surprise us, from advanced to primitive.

My answer to this thread, like others, is simply stated as follows;

> what is the analog design logic of the structure between the two arrows in the photo below?

1. Why do you assume this design is good? Please cite your source in future to avoid garbage in> garbage out on the web.
2. This circuit is called a "signal conditioner" and is Analog not Logic.

Logic uses rules of truth, Analog comes from transistor "101" standard configurations of CE, CC, CB (common emitter etc.)​

3. This question ought to have the purpose behind the schematic with the question and at least its purpose.
4. This circuit has many symptoms of a "rookie design" with unusual arrangements and resistors (trial and errors)

5. My analysis:
(A to B) Source large signal, > partial dV/dt Limiter with negative DC bias
(B to C) > partial dV/dt with high gain CE amplifier
(C to D) R (?? values) divider with fixed attenuator and variable pot attenuator to lower signal and impedance with -ve output
(D to Q4/Q3-e) CC buffer or "emitter follower" to reduce Rout from 1k to 1k /hFE for negative swing, Rout = R29 for positive swing
(Q4/Q3-e to E D = OUT_GRF) R27 + R33 matches ~ Rout for -ve swing only, Load = unknown but looks like a "sub-optimal" driver

Output is similar to a Darlington emitter follower buffer yet asymmetric impedance, perhaps to (poorly) control skew of rising and falling edges.

re Diode AC resistance, r
As you may know, this is called "incremental resistance" or ΔR [Ω] or Rs or rπ in Vbe or rs. These have common interpretations in electronic language where the minimum value is limited by "bulk" resistance due to size of the chip and If.

We know ΔR rises exponentially in diodes with smaller than rated currents.

This design begs many questions about purpose and specs which are more important than this question.

View attachment 189751

--- Updated Apr 4, 2024 ---

If you have a better question with a purpose or functional spec. , pls ask.