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In an SRAM, if the BL and its complement are precharged to half of Vdd, then what is the voltage drop on the bit line if the cell stores a 0 and if the 6T SRAM cell stores a 1?. If it is a 1 stored at the output , then the nmos transistor is on and it connects the bit line to the ground making the voltage from 0.5 to 0.45V. Is this right? What happens to the complement? Does it rise to 0.54V since it is connected to 0(Opposite of output)?