[SOLVED] Synthesis and Power Analysis flow for SRAM

[abhishektyagi]

Hi Everyone,
I am writing this post to ask for everyone's help in clarifying the mystery that is ASIC Synthesis flow. Maybe not everyone agrees with me that the flow is unclear, but as someone who started with it on their own, I still think there are so many variables that it is difficult to do even the simplest of tasks.

NOTE: I have listed possible odd warnings/behaviours for each part of the flow

Goal: I am trying to understand how much power it takes to do read and write operations in SRAM. But I am not getting any switching power during power analysis
Flow:
1) I am using ARM Artisan Compiler to generate SRAM Macro using views such as .lib and .v files
2) I instantiate the .v module in another system verilog file which is going to be my topmost module. I then write a small test bench to do the read and write operations.
3) I use VCS to compile and simulate this behavioral model.
4) I use Design Compiler to carry out the synthesis
5) And lastly, I am using PrimeTime to do power analysis.

I am breaking down the flow here, along with snippets of code for your reference.

VCS Simulation
For this part, I am using the following command:

vcs -sverilog  stdcell.v sram_top.sv sram_sp_uhde.v -top sram_tb testbench.sv -debug_all -full64 +vcs+dumpvars+vcd_file.vcd +define+INITIALIZE_MEMORY -sdfverbose -override_timescale=1ns/1ps -xprop=tmerge -o simv

stdcell.v : is a file that i get from my 7nm library
sram_top.sv: Topmost module where the SRAM Macro is instantiated
sram_sp_uhde.v: SRAM Macro verilog file generated by memory compiler
testbench.sv: Test bench file

I pass this part with no errors and required behavior

Synthesis using Design Compiler
My tcl script for this part looks like the following:

set_app_var search_path {/home/seas/guest/atyagi2/npu/synthesis/sram1block /home/seas/guest/atyagi2/npu/synthesis/db /home/seas/guest/atyagi2/npu/synthesis/memComp }
set_app_var symbol_library class.sdb
set_app_var target_library /home/seas/guest/atyagi2/npu/synthesis/db/sch240mc_cln07ff41001_base_svt_c11_tt_typical_max_0p75v_85c.db
set_app_var link_library /home/seas/guest/atyagi2/npu/synthesis/sram1block/library.db
read_file -format sverilog {/home/seas/guest/atyagi2/npu/synthesis/sram1block/sram_top.sv}
analyze -library WORK -format sverilog {/home/seas/guest/atyagi2/npu/synthesis/sram1block/sram_top.sv}
elaborate SRAM_TOP -library WORK
uplevel #0 { report_port }
change_selection [get_ports [list clk] ]
create_clock -name "clk" -period 250 -waveform { 0 3  }  { clk  }
set_input_delay 1.0 [remove_from_collection [all_inputs ] clk] -clock clk
set_output_delay 2.0 [all_outputs] -clock clk
set_max_area 0
set_clock_gating_style -minimum_bitwidth 2
set_operating_conditions -library sch240mc_cln07ff41001_base_svt_c11_tt_typical_max_0p75v_85c tt_typical_max_0p75v_85c
set_clock_uncertainty -setup 0.500 [all_clocks]
set_clock_uncertainty -hold  0.000 [all_clocks]
set_max_transition 0.500 [current_design]
set_wire_load_model -name Medium -library sch240mc_cln07ff41001_base_svt_c11_tt_typical_max_0p75v_85c
compile_ultra > ./sram1block.log
report_timing > sram1block_timing.rep
uplevel #0 { report_area } > sram1block_area.rep
write -format verilog -hierarchy -output ./sram1block.v
write -format ddc     -hierarchy -output sram1block.ddc
write_sdc -nosplit sram1block.sdc
write_sdf sram1block.sdf
exit

NOTE: library. db is the file that I generate from the .lib file I get from the SRAM compiler

Other than the following warning, nothing seems out of the ordinary:

Warning: Overwriting design file '/home/seas/guest/atyagi2/npu/synthesis/sram1block/SRAM_TOP.db'. (DDB-24)

But, I also get the following output on the screen:
Pin Wire Max Max Connection
Port Dir Load Load Trans Cap Class Attrs
--------------------------------------------------------------------------------
A_[0] in 0.0000 0.0000 -- -- --
A_[1] in 0.0000 0.0000 -- -- --
A_[2] in 0.0000 0.0000 -- -- --
A_[3] in 0.0000 0.0000 -- -- --
A_[4] in 0.0000 0.0000 -- -- --
A_[5] in 0.0000 0.0000 -- -- --
A_[6] in 0.0000 0.0000 -- -- --
A_[7] in 0.0000 0.0000 -- -- --
A_[8] in 0.0000 0.0000 -- -- --

I am not sure if Pin/Wire loads are supposed to be zero or not.

Power Analysis using Prime Time
Here is the tcl script I am using for power calculations:

set power_enable_analysis TRUE
set_app_var search_path {/home/seas/guest/atyagi2/npu/synthesis/sram1block /home/seas/guest/atyagi2/npu/synthesis/db /home/seas/guest/atyagi2/npu/synthesis/memComp }
set_app_var target_library /home/seas/guest/atyagi2/npu/synthesis/db/sch240mc_cln07ff41001_base_svt_c11_tt_typical_max_0p75v_85c.db
set_app_var link_library /home/seas/guest/atyagi2/npu/synthesis/sram1block/library.db
read_verilog /home/seas/guest/atyagi2/npu/synthesis/sram1block/sram1block.v
current_design SRAM_TOP
link_design
read_saif /home/seas/guest/atyagi2/npu/synthesis/sram1block/saif_file.saif -strip_path "sram_tb/dut"
#read_vcd /home/seas/guest/atyagi2/npu/synthesis/sram1block/vcd_file.vcd -strip_path "sram_tb/dut"
create_clock clk -name clk -period 250
update_power
report_power > power_report.rep

NOTE: Here dut is not the SRAM Macro, but a wrapper on top of it

When I run PrimeTime with this script, I get following warnings:
Warning: Unable to resolve reference to 'TIEHI_X1N_AH240TS_C11' in 'SRAM_TOP'. (LNK-005)
Warning: Unable to resolve reference to 'TIELO_X1N_AH240TS_C11' in 'SRAM_TOP'. (LNK-005)
Information: Creating black box for U5/TIEHI_X1N_AH240TS_C11... (LNK-043)
Information: Creating black box for U6/TIELO_X1N_AH240TS_C11... (LNK-043)

Along with this, I get a table like this

instance dumpaddr None Found
instance dumpmem None Found
instance failedWrite None Found
instance loadaddr None Found
instance loadmem None Found
instance uDQ0 None Found
instance uDQ1 None Found
instance uDQ10 None Found
instance uDQ11 None Found
instance uDQ12 None Found
instance uDQ13 None Found
instance uDQ14 None Found
instance uDQ15 None Found
instance uDQ16 None Found
instance uDQ17 None Found


I am not sure why the instances are not found.

The final report I get is like the following:

Internal Switching Leakage Total
Power Group Power Power Power Power ( %) Attrs
--------------------------------------------------------------------------------
clock_network 0.0000 0.0000 0.0000 0.0000 ( 0.00%) i
register 0.0000 0.0000 0.0000 0.0000 ( 0.00%)
combinational 0.0000 0.0000 0.0000 0.0000 ( 0.00%)
sequential 0.0000 0.0000 0.0000 0.0000 ( 0.00%)
memory 1.819e-05 0.0000 2.829e-04 3.011e-04 (99.99%)
io_pad 0.0000 0.0000 0.0000 0.0000 ( 0.00%)
black_box 0.0000 1.687e-08 0.0000 1.687e-08 ( 0.01%)

Net Switching Power = 1.687e-08 ( 0.01%)
Cell Internal Power = 1.819e-05 ( 6.04%)
Cell Leakage Power = 2.829e-04 (93.96%)
---------
Total Power = 3.012e-04 (100.00%)

I am curious why the Switching power is that low (the unit is mW, btw) for a case of single read and write and why is it black box?

 

[ThisIsNotSam]

blackbox means you instantiate something that the tool does not know what it is. I think you have some issue with std cell library because the tool cannot find TIE cells.

switching power and internal power make sense when we are talking about standard cells. for SRAM not so much. the reason it appears to be that low is because your frequency is very low. leakage is dominating the power consumption. I think you have a 250ns clock period, no?

 

[abhishektyagi]

blackbox means you instantiate something that the tool does not know what it is. I think you have some issue with std cell library because the tool cannot find TIE cells.

switching power and internal power make sense when we are talking about standard cells. for SRAM not so much. the reason it appears to be that low is because your frequency is very low. leakage is dominating the power consumption. I think you have a 250ns clock period, no?

Yes, my clock period is really low. That could be the reason for the low switching frequency

I do wanna clarify if you think the tool is able to recognize the SRAM .db file or not. Or is that why there is black-box power?

And how do you think i can fix the issue of looking for TIE cells in my std cell library?

 

[ThisIsNotSam]

I believe the .db file is being found and read correctly, otherwise you would get 0/0/0 on the memory-related row of the power consumption. yet, something else is still missing. check your logs, the tool must be complaining about some files/info missing