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Spice simulation of Gate Level Netlist

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akash singh

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I have post synthesis netlist generated by design compiler. I want to perform spice analysis on this netlist. I don't know how to generate spice netlist and which tools to use. Can someone tell me how spice analysis is performed on the gate level netlist?

Thanks in advance
 

kirteshmiet

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Hi Akash you can use HSPICE(synopsys tool) or Virtuoso UltraSim Simulator (cadence tool) for your analysis. these tools can convert netlist into spice also.
 

akash singh

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I'm using UMC free libraries. Can you tell me which files to use as spice models and libraries for standard cells used in the netlist.
 

kirteshmiet

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Hi Akash,

you have to give spice models for macros , ios , std cells. spice files will be having extension as .cdl and libs will be same as synthesis i guess.
 

akash singh

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Can you point me to some tutorial.

Hi Akash,

you have to give spice models for macros , ios , std cells. spice files will be having extension as .cdl and libs will be same as synthesis i guess.
 

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