Spice simulation of Gate Level Netlist

[akash singh]

I have post synthesis netlist generated by design compiler. I want to perform spice analysis on this netlist. I don't know how to generate spice netlist and which tools to use. Can someone tell me how spice analysis is performed on the gate level netlist?

Thanks in advance

 

[kirteshmiet]

Hi Akash you can use HSPICE(synopsys tool) or Virtuoso UltraSim Simulator (cadence tool) for your analysis. these tools can convert netlist into spice also.

 

[akash singh]

I'm using UMC free libraries. Can you tell me which files to use as spice models and libraries for standard cells used in the netlist.

 

[kirteshmiet]

Hi Akash,

you have to give spice models for macros , ios , std cells. spice files will be having extension as .cdl and libs will be same as synthesis i guess.

 

[akash singh]

Can you point me to some tutorial.

Hi Akash,

you have to give spice models for macros , ios , std cells. spice files will be having extension as .cdl and libs will be same as synthesis i guess.