specify clock input pin

[buenos]

hi

how to specify clock input pin at xilinx spartan-2 and ISE?

the PACE doesnt let me to set "P80" as a pin for the CLKIN port of the top VHDL module. It lets me to set "Pxx" for the other ports.
At the Pin-80, there is a GCLK0 input pin.

spartan-2 has some pins as dedicated GCLK pins. Spartan3 has some pins: IOxxxx/GCLKy

 

[echo47]

Maybe your version of PACE is broken. Be sure you have the latest ISE service pack.

Here are some alternatives:

You can put a LOC constraint into your UCF file:
NET "CLK" LOC="P80";

Or put a LOC attribute into your HDL file:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity top is
  port
  (
    CLK : in  std_logic;
    Q   : out std_logic_vector(3 downto 0)
  );
  attribute LOC : string;
  attribute LOC of CLK : signal is "P80";
end top;

architecture archi of top is
  signal tmp: std_logic_vector(3 downto 0) := "0000";
begin
  process (CLK)
  begin
    if (rising_edge(CLK)) then
      tmp <= tmp + 1;
    end if;
  end process;
  Q <= tmp;
end archi;

For more alternatives, see "LOC" in your ISE Constraints Guide.