Sizing the MOSCAP transistor for specified capacitance value

[Anachip]

Hi,

I have a question here. Let say i wanna have a capacitor with the design of MOSCAP transistor, what is the actual way of doing that. Is drain, bulk and source is connected together and gate is by itself, so it has only 2 terminal which behave as a 2 plat capacitors and which MOS is good to do this (NMOS or PMOS). Is there any specific calculation to size the transistor for the specified capacitance value. Currently im using Cadence to measure the value of the MOSCAP by looking at the total gate capacitance (Cgg) under DC operating options.

Thanks,
Anachip

 

[hnejati]

moscap

I suggest the Fundamentals of Modern VLSI Devices(by Taur and Ning) book with a chapter on MOSCAP.

 

[williamy]

measuring moscap

for n-well process, the pmos is better choice

 

[cmos_dude]

cadence cgg parameter

Hi,

I have a question here. Let say i wanna have a capacitor with the design of MOSCAP transistor, what is the actual way of doing that. Is drain, bulk and source is connected together and gate is by itself, so it has only 2 terminal which behave as a 2 plat capacitors and which MOS is good to do this (NMOS or PMOS). Is there any specific calculation to size the transistor for the specified capacitance value. Currently im using Cadence to measure the value of the MOSCAP by looking at the total gate capacitance (Cgg) under DC operating options.

Thanks,
Anachip

Yes the drain, source and the bulk are shorted together to obtain the 2 terminal cap with the gate and bulk (well).
For sizing the MOS, u need to look into the design document by the foundry where you have the values of parameters like Accumulative Cap, Gate Leakage, min cap, max cap, min width and min length.

The design length and width are kept short enough to minimize the effect of n-well series resistance on the frequency response of the capacitor and wide enough to minimize the effect of the polysilicon series resistance. You can have multiple NFET's in the well with connected gates to have a better layout.
Gate leakage should be considered when using the thin-oxide decoupling capacitor.

Hope this helps you!!!

--cmos_dude