sdf annotator user guide
i have checked the path again and it's ok
sdf is generrated after sta with paramistics file using primetime
does simulation tool can report some indications if sdf file has some syntax errors?
In compared with sdf generated after systhysis, there are a litter changes just like clock buffers models and no any other differences
and the gate level-simulation is ok now, so what should i check the protential error?
weather the error is caused by the process of P&R or not and i have no experience for this
thanks, aji
regards
drizzle
Added after 1 hours 8 minutes:
hi aji
when i want to check the transcript log earlierly, the log can not be stop at the error part with break.
which comment can deal with it?
thanks
Added after 17 minutes:
the error report
verror 3251
#
# vsim Message # 3251:
# Either the specified port or the instance containing the port could
# not be found in the design. Verify that the SDF file is being applied
# at the correct level of the design.
# [DOC: QuestaSim User's Manual -
# Standard Delay Format (SDF) Timing Annotation Chapter]
#