Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

simulation problem with sdf

Status
Not open for further replies.

drizzle

Member level 3
Joined
Jun 7, 2006
Messages
56
Helped
2
Reputation
4
Reaction score
0
Trophy points
1,286
Activity points
1,667
vsim-sdf-3251

it is the post-simulation after P&R completed.

when i do post-simulation, a error occurs which interrupt the simulation
the log lists here:
# ** Error: (vsim-SDF-3445) Failed to parse SDF file "D:/test/move/moving_picture.sdf".

i have no idea about what problem SDF file may have?
help me please!

regards
drizzle
 

vsim-sdf-3445

drizzle said:
it is the post-simulation after P&R completed.

when i do post-simulation, a error occurs which interrupt the simulation
the log lists here:
# ** Error: (vsim-SDF-3445) Failed to parse SDF file "D:/test/move/moving_picture.sdf".

i have no idea about what problem SDF file may have?
help me please!

regards
drizzle

Does the file/path valid? Do

Code:
ls "D:/test/move/moving_picture.sdf"

It is also be possible that your SDF file has some syntax error, how was this SDF file generated?

Use the verror utility, here is what it says for this error:

$ verror 3445

vsim Message # 3445:
One or more problems occurred during parsing of the SDF file. Look
earlier in the transcript for error messages that indicate what the
problems are.
[DOC: ModelSim User's Manual -
Standard Delay Format (SDF) Timing Annotation Chapter]

Ajeetha, CVC
www.noveldv.com
 

    drizzle

    Points: 2
    Helpful Answer Positive Rating
sdf annotator user guide

i have checked the path again and it's ok

sdf is generrated after sta with paramistics file using primetime
does simulation tool can report some indications if sdf file has some syntax errors?

In compared with sdf generated after systhysis, there are a litter changes just like clock buffers models and no any other differences

and the gate level-simulation is ok now, so what should i check the protential error?

weather the error is caused by the process of P&R or not and i have no experience for this

thanks, aji

regards
drizzle

Added after 1 hours 8 minutes:

hi aji

when i want to check the transcript log earlierly, the log can not be stop at the error part with break.

which comment can deal with it?

thanks

Added after 17 minutes:

the error report
verror 3251
#
# vsim Message # 3251:
# Either the specified port or the instance containing the port could
# not be found in the design. Verify that the SDF file is being applied
# at the correct level of the design.
# [DOC: QuestaSim User's Manual -
# Standard Delay Format (SDF) Timing Annotation Chapter]
#
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top