Simulation of multiple-metal stacked inductors with EM solvers

[Hamid.Kiumarsi]

Suppose that I want to design inductors on a CMOS process with 12 metal layers.
To increase the quality factor, I am stacking M12 (12th metal) with M11 and M10 using lots of via-holes.
The problem is how to simulate this structure with EM solvers
Simulating the real case which has via-holes with real sizes is a time consuming simulation and sometimes it's impossible.
As a result many engineers resort to use a big via-hole with the same size as the metals (M12, M11 and M10 in this case).

However if big via-holes are used then the structure will not represent the actual inductor precisely.
In the real case via-holes cannot carry horizontal currents but if we assume that we have big via-holes
with the same size of metal lines, then solver will assume that they can carry also horizontal currents.

What do you suggest for this case?

 

[volker_muehlhaus]

In the real case via-holes cannot carry horizontal currents but if we assume that we have big via-holes
with the same size of metal lines, then solver will assume that they can carry also horizontal currents.

That's an important aspect. You can solve it by connecting the layers with vias at the beginning and at the end, and every 90° or so. The other vias in between don't have much effect anyway.

 

[Hamid.Kiumarsi]

That's an important aspect. You can solve it by connecting the layers with vias at the beginning and at the end, and every 90° or so. The other vias in between don't have much effect anyway.

If other vias in between don't have much effect, how come it's stated in many articles that we should use as much as via for stacking.
These vias have large resistances and therefore by using many of them (in parallel) we can reduce this resistance.

How we can solve this issue?

 

[volker_muehlhaus]

If other vias in between don't have much effect, how come it's stated in many articles that we should use as much as via for stacking.
These vias have large resistances and therefore by using many of them (in parallel) we can reduce this resistance.

Try it. You will see that because of skin effect, the inner vias have almost no current.

The vias at the beginning and at the end, where the current distributes to the metal layers, are important. The other vias have very small current. Simulate and check the via currents, then simulate with/without these vias and compare the results.

 

[Hamid.Kiumarsi]

When the port is very close to the via, it means that we have placed our port close to the first discontinuity of the circuit.
If the first discontinuity is close to the port, then results of say Momentum will not be very accurate (but still accurate).
Personally I do de-embedding to remove this effect, that is, I use a longer feeding point and then de-embed out that extra line but sometimes results I get are not reasonable.

Do you think we should care about this issue or not?

 

[volker_muehlhaus]

The stacked metal via method that I described above works fine, and I have used it many times. But I use Sonnet EM, so I can not comment on the Momentum port question.