Inaccuracy between EM Sim and fabrication

[Orey]

Hello all,

I do fabricate rectifier using SMD diode and capacitor for a project and I found a lot of inaccuracy between simulation and fabrication. For example, I do have a shift as visible here (blue is experimental):

https://imgur.com/PkwGQmr

I tried to simplify my circuit to see if it's coming from my substrate definition or components and find similar results when I look on the S11 but not on the Smith Chart...

https://imgur.com/9CA1Mzb

Is it due to some simulation parameters I don't define properly ?

Thanks

 

[BigBoss]

Such errors may come from different sources like ;
-Manufacturing Errors
-Model Errors
-Simulation Errors
-Calibration Errors
Post your substrate definition window here. Let's see how you defined your substrate.
Also, if you can, post archived format of your project here. (do not zip the whole directory, make it archived with extension *.7zads)

You have to take all above into account and DO a Monte Carlo simulations with appropriate defined variables. You will see how the circuit response may shift.

 

[PlanarMetamaterials]

Welcome, Orey!

What substrate are you using? What are the tolerances of the manufacturing process?
My guess is that you are using a type of FR-4; in this case the observed shifts are likely within the variances of the dielectric constant and possibly the fabrication process as well.

The ripples in the first plot of experimental data indicates impedance mismatching or incorrect port de-embedding -- have you double-checked the calibration of the VNA and the setup?

 

[Orey]

Here is my substrate definition (and its datasheet ):

https://imgur.com/Aq5G9R1

I have calibrated the VNA also and the waves are disappearing, nevertheless, we can still observe this shift.

And the archive of my work:

 

[volker@muehlhaus]

In your second screenshot, the mesh does not show the via !? Is the via included properly in your EM stackup?

Have you checked how S11 varies with input power?

--- Updated Jan 19, 2024 ---

and find similar results when I look on the S11 but not on the Smith Chart...

This is only a phase shift from different feed line length.

 

[Orey]

I didn't put any via on the second design. Shall I modify the feed line length through the port definition using a TRL with a length of my SMA connector?

 

[volker@muehlhaus]

Shall I modify the feed line length through the port definition using a TRL with a length of my SMA connector?

Yes, this will rotate the entire curve in Smith chart.

 

[BigBoss]

The ripples in the first measurement has called my attention. Why there are so many ripples there ? It's a simple rectifier circuit and there is nothing to cause an oscillation. Are you sure that you did a good calibration ?? Or are there any impacting signal sources ??
Additionally, meshing density seemed to me a bit coarse. Using a second layer being as GND is not a good approximation unless it has a particular purpose. This circuit uses simple Signal-Substrate-GND configuration, this is not very usual. I'd use standard GND layer for this circuit.
The first attempt had to be to match simulation and measurement results, second degree simulation could be done in a 3D EM simulator with all the details there.

 

[vfone]

In this type of detector, S11 varies with input power. DC biasing the diodes improve the detector performance and reduce the differences between simulated an measured results.

 

[PlanarMetamaterials]

I have calibrated the VNA also and the waves are disappearing, nevertheless, we can still observe this shift.

And the archive of my work:

Having taken care of the ripples in calibration, at this point, I highly suspect the deviations are just the use of FR4. The relative permittivity of the material can typically vary widely from ~3.8 to ~4.8, and is also spacially inhomogenous and varies with frequency (note that the datasheet defines 4.7 at 1 MHz [!]). It is also fairly lossy, and the losses increase with frequency and are substantial at ~4 GHz.
Typically, FR4 is not commonly used above 1 GHz due to this poor performance.

I would try varying the substrate parameters to see if the simulation better matches your experimental data -- this would be a good indication that the substrate is to blame.

 

[Orey]

Hello all,

here are some updates (red is simulation blue is experimental).

First, this is my simulations parameter (my frequency plan is DC to 6 GHz and adaptive type). I also add a TML (zero length) with a ref offset of -7 mm for the input port:

Then, this is my results with my VNA calibrated:

• A simple circuit without via, everything seems fine with the TML zero length.
  • 
• A circuit with VIA I add:
  • There are some difference on the Smith Chart
  • 
• And last one, the rectifier with all the components: here the difference is huge between both looking on the smith chart:
  • 

Is it because my VIA are not well defined for the simulation that I have such difference and then using components such as the schottky diode will enhance this error? In terms of fabrication, I do mechanical engraving and the dimension are the same as on ADS.

Best,

 

[volker@muehlhaus]

Your second case with the via shows a 25° phase offset at 4GHz, most likely this is a difference in calibration plane measured vs. simulated. After removing that offset length, agreement is reasonable. An of course, such a phase offset/difference in feed line length would have no effect on your rectifier operation.

Regarding the difference in the third case with rectifier components, see post #9.

 

[vfone]

Instead of a shorted stub (with a via at the end), try using an open stub, which will have about half of the length of the shorted stub.
Being shorter, you may get less variation between simulated and measured results, due to PCB variations.

 

[volker@muehlhaus]

you may get less variation between simulated and measured results, due to PCB variations.

Possible, but the differences of the PCB-only testcases are small, and the large difference in the last case (with diode) is NOT caused by PCB tolerances.

Instead of blaming PCB tolerances, @Orey should investigate the obvious issue: non-linear response of the diode => load impedance that varies with input power

 

[vfone]

Varying the load impedance from the Schottky diodes will not get much shift in frequency of S-parameters.
But varying a bit the Er of the substrate you will get a lot of shift in frequency. So you have to find one-by-one which is the most sensitive printed component to Er variations. I mean one-by-one, because is very well known that various types of printed components have different sensitivity to Er variations.

 

[volker@muehlhaus]

Varying the load impedance from the Schottky diodes will not get much shift in frequency of S-parameters.

The layout is an impedance matching network and load impedance (depending on power and/or bias) will have a strong effect.

But varying a bit the Er of the substrate you will get a lot of shift in frequency.

Yes, but we don't need to guess here because measured vs. simulated results are already available: the frequency shift for the 3 GHz resonance is 1%, which means that PCB permittivity is approx 2% lower than simulated. This is only a small effect for this specific case.

The additional phase shift shown above is not caused by PCB permittivity, this is a difference in measurement plane.

Let me repeat: the layout-only testcase agreement is quite good, and only the layout + diode testcase shows big difference in impedance, which is not explained by phase offset on the 50 Ohm feedline.

 

[Orey]

Hello,

I am updating this thread with new experiments results I have. I am suspecting that the frequency shift is due to the VIAs of my circuit. I did 3 different circuits:

1. case: A line with an open stub and the diode I am using (HSMS 285B).
2. case: A line with a short stub and the diode I am using
3. case : A line with a short stub and the diode I am using + the second diode is short circuited with a stub.
   

As it can be seen in the simulation (red) vs experimental (blue) results, the shift appears only when the diode is short circuited. Is it due to the simulation? Or fabrication? In my lab, we do VIAs by drilling the fr4 and then put some copper strip that we solder with the ground or we put some silver conductive paste and put the circuit into the oven. In the picture bellow, we use copper strip.

Thank you

 

[volker@muehlhaus]

the shift appears only when the diode is short circuited

What model(s) did you use for simulation of the diodes? Does your simulation use the correct bias point (current) for each of the two diodes, including the shorted diode?

 

[Orey]

I am using the diode model described in the datasheet:

And then, I co-simulate everything in a schematic using the diode component and the board EM-model. How can I check that the correct bias point is use during my LSSP simulation?

 

[volker@muehlhaus]

How can I check that the correct bias point is use during my LSSP simulation?

The model is fine, I wasn't sure if you are using S2P data at some fixed bias current.
Also, the wire for the vias should be "good enough" if you add some more solder around the large via at the wide stub.