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simulating tetramax atpg patterns with vcs

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honey13

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I am using tetramax for atpg. I want to simulate the patterns in vcs.
Do i need to include any switch while saving patterns or can i use them just by saving as write_patterns file.v
someone help me please.
 

TonyLS

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I am using tetramax for atpg. I want to simulate the patterns in vcs.
Do i need to include any switch while saving patterns or can i use them just by saving as write_patterns file.v
someone help me please.
You need the -format and either -par or -se switches. In the past I've always used verilog_single_file format, but not sure what you would use for vcs. The -par or -se corresponds to the type of patterns you want, par = parallel, se = serial.

Serial patterns take a very long time to simulate since there is one vector for every shift pulse to load and unload the chains. Par patterns are much faster since they parallel load all scan flops, essentially bypassing the shift in/out of the long scan chains. The following was my flow when I was doing a lot of DFT work:

1) create SER patterns with a small amount of vectors: Simulate this to verify the scan chains.

2) create all patterns in PAR format: Simulate these patterns to verify the entire design.

3) create all patterns in SER format to hand off to the ATE test engineer for manufacturing test. I would run sims on these patterns after handoff, while the chip was in fab. It wasn't a gate for tape out.

Hope this helps
 

avinashch

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vcs is just a verilog simulator by synopsys just like you have modelsim and xilinx. all you need to do is include $vcdpluson; in your testbench after you declare your initials and simulate your vectors along with the testbench and the verilog gated models and it will generate you a vpdvcd file for which you can see the generated waveform in the dve interface.
 

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