Simple doubt on cadence Virtuoso

[ramesh441]

cadence virtuoso 6

Can anyone say me...

How to tap LFSR initially i.e how to seed the values into the circuit
when we design through schematic in Virtuso???

How could I design a circuit that for 10 clock pulses my input has to get changed.
In HDL we can write code but how could it be done in schematic????

 

[hqqh]

Hi,

if you have RTL-code of your HDL you simpy have to synthesize it and import it into cadence DFII. Then you have a cell and a view of e.g. your verilog gate netlist and can instantiate it in another schematic.

Regards
hqqh