Silicon Ensemble + Report RC

Hi,

I have a routed design (using silicon ensemble) to begin with to which
I make modifications like adding additional logic (nets and components)
afterwhich I do incremental placement (ECO) and re-route using the 'incremental-final-route' option in silicon ensemble. Is it
possible to estimate congestion - in view of new nets being added? How do I quantify congestion? Is it possible to get capacitance information - using the dspf files that are written out? What do I look for either in a .dspf or .rspf file?

How do i use the HyperExtract option while doing report RC - will that
help?

I currently have def and dspf file of design before modification and
def and dspf file of design after modification.

Any help would be appreciated.

Thanks,
Suresh

As for congestion.. I'm not overly sure as i've only used SE with older 3 metal 0.5um libraries which congestion was never a issue..

As for delays, etc.. i just create a SDF and bring it into the verilog simulator to see timing..

REPORT DELAY FILENAME "routed.sdf" ;

jelydonut