[SOLVED] Signal Count cannot be synthesized

[kikikrunch]

Hi guys

Need a little help here as I'm new to VHDL. I kept getting the error of

ERROR:Xst:827 - "C:/Documents and Settings/Administrator/Desktop/temp/blink_led/simple_count.vhd" line 58: Signal count cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release.

This is my code. Any help would be very much appreciated.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity simple_count is
    Port ( clock : in  STD_LOGIC;
           enable : in  STD_LOGIC;
			  dir: in	STD_LOGIC;
			  reset: in	STD_LOGIC;
           leds : out  STD_LOGIC_VECTOR (3 downto 0));
end simple_count;

architecture Behavioral of simple_count is

signal count: std_logic_vector (3 downto 0) := "0000";
signal clk_div: std_logic;
begin

clk_divider : process(clock)
variable clk_count: std_logic_vector(23 downto 0) := (others => '0');
begin
	if clock'event and clock = '1' then
	clk_count := clk_count+1;
	clk_div <= clk_count(23);
	end if;
end process;


process (clk_div) 
variable reset_var: std_logic := '0';
variable dir_var: std_logic := '0';
begin

		if reset='1' then
			reset_var:='1';
			elsif dir='1' then
				dir_var:= not dir_var;
		end if;
				
		-- start of reset function
		if (reset_var='1' and dir_var='1') then 
			count<="1111";
			reset_var:='0';
			elsif (reset_var='1' and dir_var='0') then
				count<="0000";
				reset_var:='0';
		end if;
		--end of reset function
		
		if (clk_div='1' and clk_div'event) then
			if (enable='0' and dir_var='0') then
				count <= count + 1;
				elsif enable='0' and dir_var='1' then
					count <= count - 1;
			end if;
		end if;

end process;

leds <= count(3 downto 0);	

end Behavioral;

 

[jrwebsterco]

You've got a few problems here.

One is that you are not using the correct expected "template" structure for describing reset as either an async or sync reset.
(if sync-reset then the conditional if's need to be inside of the edge-clocked area, but if async-reset then reset is missing from the process statement)

A few suggestions ...
1) Take a look at the Xilinx ISE language templates under Edit->Language Templates, then expand VHDL->Synthesis Constructs->Process->Posedge Clocked, and look at the code examples for the different types of flop descriptions.
2) Much of this is also available under Help->Software Manuals, and then click into the "Synthesis and Simulation Design Guide" and look at chapter 5 "Coding for FPGA Device Flow" under subsection "Registers in FPGA Design".
3) You might find some of the following links helpful, but maybe they do not give good synthesis examples: https://www.fpga4fun.com/HDL tutorials.html

 

[TrickyDicky]

the reset "function" (btw, its not a function) needs to bee in the same if block as the clock.
PS. Creating a divided clock like this is not recommended. Read up on clock enables instead.

 

[kikikrunch]

Thanks a lot! I've solved it by using the standard template. =)