[SOLVED] Signal Count cannot be synthesized, bad synchronous description.

[Ata-Va]

Hello
I have the same problem. I'm new to VHDL. I tried to find what is wrong but I have no idea. while compiling whole project I get "Signal Count cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release." well I define Count as a variable not a signal but I dont see what's wrong.
and also if some one how can i measure speed of Quadrature_Encoders using 4X Encoding State Transition. the blow code is for 4X Encoding State Transition which Iam not sure even if it fixes will it function correctly or not.
thx everbody


architecture Behavioral of Quadrature_Encoders is
begin

process(A,B)
Variable Count : Integer Range -128 to 128:=0;
begin
if (A'event AND A = '1')then
if (B = '0') then
Count:=Count+1;
elsif (B='1') then
Count:=Count-1;
end if;
end if;

if (A'event And A='0') then
if (B = '0') then
Count:=Count-1;
elsif (B='1') then
Count:=Count+1;
end if;
end if;

if (B'event AND B = '1') then
if (A = '0') then
Count:=Count-1;
elsif (A='1') then
Count:=Count+1;
end if;
end if;

if (B'event AND B = '0') then
if (A = '0') then
Count:=Count+1;
elsif (A='1') then
Count:=Count-1;
end if;
end if;
end process;


end;

 

[barry]

You have multiple clocks inside a single process, and multiple assignments to a single variable. It's not clear WHAT you are trying to do here, but whatever it is, it's not going to work.

 

[Ata-Va]

- - - Updated - - -

if you check this site"http://tutorial.cytron.com.my/2012/01/17/quadrature-encoder/"here they are 4 ways suggested to measure the position of quadrature-encoder the best way which has a low tolerance is "4X Encoding State Transition" as you see in the figure i wanna Implement the code in vhdl.

I change it a little the code is blow


architecture Behavioral of Quadrature_Encoders is
begin

process(A,B)
Variable Cnt : Integer Range -128 to 128:=0;
begin
if (A'event AND A = '1')then
if (B = '0') then
Cnt:=Cnt+1;
elsif (B='1') then
Cnt:=Cnt-1;
end if;
elsif (A'event And A='0') then
if (B = '0') then
Cnt:=Cnt-1;
elsif (B='1') then
Cnt:=Cnt+1;
end if;
elsif (B'event AND B = '1') then
if (A = '0') then
Cnt:=Cnt-1;
elsif (A='1') then
Cnt:=Cnt+1;
end if;
elsif (B'event AND B = '0') then
if (A = '0') then
Cnt:=Cnt+1;
elsif (A='1') then
Cnt:=Cnt-1;
end if;
end if;
end process;


end;

 

[TrickyDicky]

But, like barry has said you cannot have 4 clocks, which you new code still tries to do. You need a single system clock and then sample A and B at the system clock rate.

 

[FvM]

It's not clear WHAT you are trying to do here, but whatever it is, it's not going to work.

I think, it is quite clear what he wants to achieve, but it doesn't work though.

The state diagram in the tutorial is O.K., but how to convert it to hardware logic respectively VHDL?

The solution is quite easy, instead of clocking registers with the quadrature decoder signals you need to refer to a sufficient fast clock. A microcontroller with hardware QEI or input change trigger does the same, it samples the inputs with it's system clock and determines the state changes.

I other words, you have to translate the quadrature decoder state diagram into a state machine.

 

[Ata-Va]

All buddy first level thx for your help,but non of these were the solution,of course as FVM said I could use state machine diagram but it has some difficulties, any how the above code worked with out any change, the problem was about the device that I selected Spartan3 as I changed it to Spartan 6 in worked.
thx every one