semiconductorman said:
No that is usally not the case with most of the synthesis tools available today . The question of synthesisable or not depends on how you define / design in hdl . I am assuming that u probably are talking about vhdl here. as long as you are trying to define combo logic with variables you are prety safe. happy 'RTL'ing
yup. i'm using vhdl. the fact is i can synthesize my code. but got many warning messages related to the variables. most of the variable registers are stucked to GND or VCC. whenever i assigned any variables := 0, then it will stuck to GND. i'vize my code. but got many warning messages related to the e checked my synthesis' tool (qu(at)rtus II) help page, but they mentioned it's whether i leave it or change it.
i think this problem makes my post-synthesis simulations fails.
should i avoid the variables initialization? or is there any other method? what is combo logic? how to define combo logic?