Should the use of variables be avoided for synthesis?

[arbalez]

how initialize variable in synthesizable verilog

is it true that we have to avoid the use of variables if we want our code able to be RTLed? thus able to be synthesized?

 

[silencer3]

variables and synthesis

Variables do get synthesized. It depends on coding.

The main difference for variables comes, when u do simulation. But i feel that for synthesis, it is ok to use variables. pls do check ur RTL after synthesis for correct RTL.

 

[Thomson]

Re: variables and synthesis

Different Logic languages may have different synthesizable guidelines, please read these guidelines based on your logic language.

Here just list the two prominent logic languages VHDL and Verilog:
<1> for VHDL, variables are mainly used to infer combinatirial logics; however if you really expect, the sequential logics can be also be generated, which is not recommended.
<2> for VErilog, there are no variables concepts. only Wire or Reg can be used. Of course, you can take reg as variables when used in processes.

The best is to refer to the synthesizalbe guidelines if you have both for VHDL and Verilog.

Thomson

 

[semiconductorman]

Re: variables and synthesis

No that is usally not the case with most of the synthesis tools available today . The question of synthesisable or not depends on how you define / design in hdl . I am assuming that u probably are talking about vhdl here. as long as you are trying to define combo logic with variables you are prety safe. happy 'RTL'ing

 

[arbalez]

Re: variables and synthesis

No that is usally not the case with most of the synthesis tools available today . The question of synthesisable or not depends on how you define / design in hdl . I am assuming that u probably are talking about vhdl here. as long as you are trying to define combo logic with variables you are prety safe. happy 'RTL'ing

yup. i'm using vhdl. the fact is i can synthesize my code. but got many warning messages related to the variables. most of the variable registers are stucked to GND or VCC. whenever i assigned any variables := 0, then it will stuck to GND. i've checked my synthesis' tool (quartus II) help page, but they mentioned it's whether i leave it or change it.

i think this problem makes my post-synthesis simulations fails.

should i avoid the variables initialization? or is there any other method? what is combo logic? how to define combo logic?

 

[arbalez]

Re: variables and synthesis

No that is usally not the case with most of the synthesis tools available today . The question of synthesisable or not depends on how you define / design in hdl . I am assuming that u probably are talking about vhdl here. as long as you are trying to define combo logic with variables you are prety safe. happy 'RTL'ing

yup. i'm using vhdl. the fact is i can synthesize my code. but got many warning messages related to the variables. most of the variable registers are stucked to GND or VCC. whenever i assigned any variables := 0, then it will stuck to GND. i'vize my code. but got many warning messages related to the e checked my synthesis' tool (qu(at)rtus II) help page, but they mentioned it's whether i leave it or change it.

i think this problem makes my post-synthesis simulations fails.

should i avoid the variables initialization? or is there any other method? what is combo logic? how to define combo logic?

finally, i realized my mistake after doing some reading. i just knew that variables and signals cannot be initialized for synthesis. i must use reset mechanism to initialize variables or signals as the code below,

if (reset = '1') then
   variablename := 0;
else
   ...
end if;

not by directly declare

begin
   variablename : integer := 0;
process (...)
...
end process;

now the synthesis process was completed without warnings of stuck-at GND, VCC or whatever. the mysteries solved. thanks all!