setup time violation in post layout simulation

[cashen224]

Dear experts

when I use ncsim for post layout simulations, the tools through some setup time violation warnings and indeed I have X states in the waveform and the total design messed up.

however, after P&R using SOC encounter, the SOC encounter shows no setup time violations with pretty large positive slack time. The Primetime tool also gives me positive slack time.

Can give me some hint/advise about what I should do to fix this? I really appreciate any helps.

 

[lostinxlation]

do you have false paths or multicycle paths with PT and SOC ?

 

[cashen224]

Hi,

Do you mean setting this: set_false_path. No I didn't do anything with it.

 

[lostinxlation]

Is the simulation with backannotation(w/ sdf) ?
if so, reading back the sdf into PT and see the timing.

OK, are you sure the clock speed you are using in simulation is the same as the timing analysis/backend ?

is timescale correct ?

 

[cashen224]

Thanks for the hint.

1) For the timescale, I checked and didn't find anything abnormal. Actually the clock period from the waveform is what I am looking for.
2) For the backannotation. Do you mean send to sdf file generated from SOCEncounter to the PT. If yes, I did so and the PT gives me positive slack time. BTW the way I generated SDF was (all performed in SOCEncounter): a. extrace RC to SPEF file and b. converted SPEF to SDF.

thanks

 

[yx.yang]

Thanks for the hint.

1) For the timescale, I checked and didn't find anything abnormal. Actually the clock period from the waveform is what I am looking for.
2) For the backannotation. Do you mean send to sdf file generated from SOCEncounter to the PT. If yes, I did so and the PT gives me positive slack time. BTW the way I generated SDF was (all performed in SOCEncounter): a. extrace RC to SPEF file and b. converted SPEF to SDF.

thanks

Is this because corss clock domain problem. Even you don't set_false_path on these points, you may set "set_clock_group" command on ASYNC clcoks.

Thanks.