Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

setup time violation in post layout simulation

Status
Not open for further replies.

cashen224

Newbie level 4
Joined
Apr 7, 2011
Messages
6
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,331
Dear experts

when I use ncsim for post layout simulations, the tools through some setup time violation warnings and indeed I have X states in the waveform and the total design messed up.

however, after P&R using SOC encounter, the SOC encounter shows no setup time violations with pretty large positive slack time. The Primetime tool also gives me positive slack time.

Can give me some hint/advise about what I should do to fix this? I really appreciate any helps.
 

cashen224

Newbie level 4
Joined
Apr 7, 2011
Messages
6
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,331
Hi,

Do you mean setting this: set_false_path. No I didn't do anything with it.
 

lostinxlation

Advanced Member level 3
Joined
Aug 19, 2010
Messages
701
Helped
197
Reputation
394
Reaction score
184
Trophy points
1,323
Location
San Jose area
Activity points
5,051
Is the simulation with backannotation(w/ sdf) ?
if so, reading back the sdf into PT and see the timing.

OK, are you sure the clock speed you are using in simulation is the same as the timing analysis/backend ?

is timescale correct ?
 

cashen224

Newbie level 4
Joined
Apr 7, 2011
Messages
6
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,331
Thanks for the hint.

1) For the timescale, I checked and didn't find anything abnormal. Actually the clock period from the waveform is what I am looking for.
2) For the backannotation. Do you mean send to sdf file generated from SOCEncounter to the PT. If yes, I did so and the PT gives me positive slack time. BTW the way I generated SDF was (all performed in SOCEncounter): a. extrace RC to SPEF file and b. converted SPEF to SDF.

thanks
 

yx.yang

Full Member level 4
Joined
May 29, 2008
Messages
236
Helped
49
Reputation
98
Reaction score
46
Trophy points
1,308
Location
ZhuHai, GuangDong, China
Activity points
2,661
Thanks for the hint.

1) For the timescale, I checked and didn't find anything abnormal. Actually the clock period from the waveform is what I am looking for.
2) For the backannotation. Do you mean send to sdf file generated from SOCEncounter to the PT. If yes, I did so and the PT gives me positive slack time. BTW the way I generated SDF was (all performed in SOCEncounter): a. extrace RC to SPEF file and b. converted SPEF to SDF.

thanks

Is this because corss clock domain problem. Even you don't set_false_path on these points, you may set "set_clock_group" command on ASYNC clcoks.

Thanks.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top