Setup and Hold violation for the same register is possible or not

[dll_fpga]

consider the the case of 2 back to back connected invertors that are placed between 2 flops ,since rise delay and fall delay can be different (in this case lets take this diffence large) so since there is a large diffence in the max path and min path.
so there is a chance for bothsetup and hold violations

do all agree with this?#

 

[yx.yang]

Yes, this maybe. But why the cell library designer will design such a gate cell?

 

[dll_fpga]

Yes, this maybe. But why the cell library designer will design such a gate cell?

so why rise delay and fall delay are almost similiar??
is it to avoid this problem??

 

[jeet_asic]

I don't think so its possible. Setup and hold violation can't happen for same path at a time. Yes , it is possible for different PVT conditions.

 

[birdy123]

yes both type of violation can be possible.. I completly agree with this.

 

[morris_mano]

I don't think so its possible. Setup and hold violation can't happen for same path at a time. Yes , it is possible for different PVT conditions.

Between two flip flop, if there is 3 combinational path with 10,6 and 1 ns delay, then setup looks at worst path that is with 10ns delay and hold looks at best path that is with 1ns delay. So, considering simple case with no clock skew, if hold timing check is 2ns, and setup timing check is 3ns with clock period of 10ns, there is possibility of both setup and hold violation. The main take away is setup and hold look at different combinational path between two sequential flops, even if both is analyzed in same PVT conditions.

 

[jeet_asic]

Thanks bro for nice explanation. But i was referring to "same path" . AFAIK setup and hold violation can't happen for same path.They can occur , but at different process corners.

Between two flip flop, if there is 3 combinational path with 10,6 and 1 ns delay, then setup looks at worst path that is with 10ns delay and hold looks at best path that is with 1ns delay. So, considering simple case with no clock skew, if hold timing check is 2ns, and setup timing check is 3ns with clock period of 10ns, there is possibility of both setup and hold violation. The main take away is setup and hold look at different combinational path between two sequential flops, even if both is analyzed in same PVT conditions.

 

[bschaitanya]

I completely agree with jeet_asic statement... setup and hold violation could occur for the same start and endpoints including same data levels at different process corners.

What ever morris_mano explained is for same start and endpoint but traversing through different logic levels.