dll_fpga
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consider the the case of 2 back to back connected invertors that are placed between 2 flops ,since rise delay and fall delay can be different (in this case lets take this diffence large) so since there is a large diffence in the max path and min path.
so there is a chance for bothsetup and hold violations
do all agree with this?#
so there is a chance for bothsetup and hold violations
do all agree with this?#