Settling time of ADPLL

[dirac16]

I am reading a paper which has proposed an ADPLL with a custom 8b TDC. Throughout the TDC design it claims the following:

To be robust in the settling transient, the 8bit TDC has a dynamic range equivalent to 2×TCKV unlike PLLs using narrow-range TDCs.

So how can a wider dynamic range make difference in the robustness of the settling time?