my sample&hold circuit takes a lot of time to arrive at steady state

[mohamis288]

Hello,

part of ADC is a Sample&Hold circuit. here is the circuit of my simple S&H circuit:

its symbol in the original circuit is shown in the following:

input signal is a 33KHz 200m volt sinusoidal wave with DC level of 300m V. sampling frequency is about 4 times of input frequency. it is used in a dual slope ADC. as shown below, output voltage of S&H circuit is in the transient state. it takes a lot of time to arrive at steady state, what can I do to overcome this problem?

 

[dick_freebird]

Where is your "hold" capacitor?

Without it, all you'll see is toggling and the switching charge on
turnoff (absent from your ideal switch model) will determine the
(alleged) "hold" voltage.

Hard full scale gate drive will give you a common mode dependent
sample pedestal voltage. Imbalance in Cdg (and if high Zin, Cgs) will
give you a charge offset too.

Put a layout-realistic hold capacitor on the output and resimulate.
Look at close-in port currents at the sample-to-hold edge for
charge imbalance and resulting pedestal.