I need to set and clear one bit in a large std_logic_vector, the position of the bit that needs to be changed is not static.
What you are trying to do is not a problem for the VHDL language, but it can be a problem if you want to synthesize it into a real circuit.
If you are going to synthesize a circuit, you should have some idea about the necessary hardware.
To set or clear individual bits in a large vector sounds simple, but it requires a lot of logic.
You would never do it like that if you designed hardware the "old" way, by drawing a schematic.
The solution is to use a RAM. It already has all the logic you need to do this in a simple way.
The "position" will be used as the address.
RAM bits are quite cheap, so if your RAM is wider than one bit, it is probably OK to only use only one of them.
A RAM with one write port and one read port should be suitable for this.
I don't know about Xilinx, but Altera can have different data widths for the read and write ports.
In your case the write port should be one bit, but you probably want the read port to be wider, so you can access several bits at once.
If you want to have all bits available at the same time (as your original code), use several RAM blocks configured for the maximum bit width on the read port.
In that case you also need a decoder to select a RAM block when you write.