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Difference between LPDDR4 single-rank and dual-rank with ECC interface

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Nov 3, 2018
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I am wondering about the difference between LPDDR4 single-rank and dual-rank with ECC interface. In the attached figure, the Memory Controller (I guess this is ZYNQ Ultrascale), and the Regular Unit and ECC Unit are shown. What are these two Regular Unit and ECC ? Is there any other chip in addition to the memory LPDDR4 ?


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1- What is the signal rank and dual rank in the LPDDR4 memories ?
2- What is the single die package (SDP) and dual die package (DDP) ?

Using an example of computer memory a single rank 64-bit ECC DIMM will have nine 8-bit wide DDRs on it (72-bits, 64-bits+8-bit ECC).
A dual rank ECC DDR would be configured as 8x16-bit+8-bit-ECC (rank 1) + 8x16-bit+8-bit-ECC (rank 2) only 1 rank is communicating on the bus at a time (the ranks are connected in parallel).

When multiple die are in a package it increase the number of ranks for that die as the packaged die are all in parallel.
Look like that ECC is just extra 8 bit for error correction.

Single die package (SDP), is one set of memory

Dual die package (DDP), is two set of memory but their data, address and control lines are in parallel within the chip but they have chip select for each die. In this way only one chip can be selected at a time which is also called a rank. This means that with dual die package, we can implement dual rank configuration. It is also to note that dual rank configuration is slower then two single rank configuration because in single rank there will be two single die per packages (SDP) and memory controller can select both at the same time.

Routing two single rank configuration will be more challenging as their will be two independent set of connections between memory controller and each SDP memory chip. Routing dual rank is bit easier as both ranks have parallel connections within in the DDP.

Is it also possible to chose or to run the memories at lower frequency if zynq soc ultra scale don't support it for example ?
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